 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| features ? full-duplex operation mode without duplex frequency offset to prevent the relay attack against passive entry go (peg) systems high fsk sensitivity: ?105.5 dbm at 20 kbaud/?109 dbm at 2.4 kbaud (433.92 mhz) high ask sensitivity: ?111.5 dbm at 10 kbaud/?116 dbm at 2.4 kbaud (100% ask, carrier level 433.92 mhz) low supply current: 10.5 ma in rx and tx mode (3v/tx with 5 dbm/433.92 mhz) data rate 1 to 20 kbaud manchester fsk, 1 to 10 kbaud manchester ask ask/fsk receiver uses a low if ar chitecture with high selectivity, blocking and low intermodulation (typical 3 db blocking 55.5 dbc at 750 khz/60.5 dbc at 1.5 mhz and 67 dbc at 10 mhz, system i1dbcp = ?30 dbm/system iip3 = ?20 dbm) wide bandwidth agc to handle large ou tband blockers above the system i1dbcp 226 khz if (intermediate frequency) with 30 db image rejection and 220 khz system bandwidth to support tpm tr ansmitters using ata5756/ata5757 transmitters with standard crystals transmitter uses closed loop fsk modulat ion with fractional- n synthesizer with high pll bandwidth and an excellent isolation between pll and pa tolerances of xtal compensated by frac tional-n synthesizer with 800 hz rf resolution integrated rx/tx-switch, single-ended rf input and output rssi (received signal strength indicator) communication to microcontroller with spi interface working at 500 kbit/s maximum configurable self polling and rx/tx protocol handling with fifo-ram buffering of received and transmitted data 1 push button input and 1 wake-up in put are active in power-down mode integrated xtal capacitors pa efficiency: up to 38% (433.92 mhz/10 dbm/3v) low in-band sensitivity change of typically 2.0 db within 75 khz center frequency change in the complete temper ature and supply voltage range fully integrated pll with low phase noise vco, pll loop filter and full support of multi-channel operation with arbitrar y channel distance due to fractional-n synthesizer sophisticated threshold control and quasi-p eak detector circuit in the data slicer 433.92 mhz, 868.3 mhz and 315 mhz withou t external vco and pll components efficient xto start-up circuit (> ?1.5 k ? worst case start impedance) changing of modulation type ask/fsk and data rate without co mponent changes to allow different modulation schemes in tpm and rke minimal external circuitry requirem ents for complete system solution adjustable output power: 0 to 10 dbm adjust ed and stabilized with external resistor, programmable output power with 0. 5db steps with internal resistor clock and interrupt generation for microcontroller esd protection at all pins (2.5 kv hbm, 200v mm, 500v fcdm) supply voltage range: 2.15v to 3.6v or 4.4v to 5.25v typical power-down current < 10 na temperature range: ?40c to +105c small 7 mm 7 mm qfn48 package uhf ask/fsk transceiver ATA5823 ata5824 rev. 4829c?rke?09/05
2 4829c?rke?09/05 ATA5823/ata5824 applications automotive keyless entry and passiv e entry go (handsfree car access) tire pressure monitoring systems remote control systems alarm and telemetering systems energy metering home automation benefits no saw device needed in key fob desi gns to meet automo tive specifications low system cost due to very high system integration level only one crystal needed in system less demanding specification for the microcontroller due to ha ndling of powe r-down mode, delivering of clock and complete handling of receive/transmit protocol and polling single-ended design with high isolation of pll/vco from pa and the power supply allows a loop antenna in the key fob to surround the whole application prevention against relay attack with full-duplex operation mode integration of tire pressure monitoring , passive entry and remote keyless entry 1. general description the ATA5823/ata5824 is a highly integrated uhf ask/fsk multi-channel half-duplex and full-duplex transceiver with low power consumption supplied in a small 7 mm 7 mm qfn48 package. the receive part is built as a fully integrated low-if receiver, whereas direct pll mod- ulation with the fractional-n synthesizer is used for fsk transmission and switching of the power amplifier for ask transmission. th e additional full-d uplex mode makes rela y attacks much more difficult, since the attacker has to receive and transmit signals on the same frequency at the same time. the device supports data rates of 1 kbaud to 20 kbaud (fsk) and 1 kbaud to 10 kbaud (ask) in manchester, bi-phase and other codes in tran sparent mode. the ata5824 can be used in the 433 mhz to 435 mhz band and the 867 mhz to 870 mhz band, the ATA5823 in the 313 mhz to 316 mhz band. the very high system integration level results in few numbers of external compo- nents needed. due to its blocking and selectivity performance, together with a typical narrow-band key-fob loop antenna with 15 db to 20 db loss, a bulky blocking saw is not needed in the key fob application. additionally, the building blocks needed for a typical rke and access control system on both sides, the base and the mobile stations, are fully integrated. its digital control logic with self polling and protocol generatio n provides a fast challenge response system without us ing a high-performance microcontroller. therefore, the ATA5823/ata5824 contains a fifo buffer ram and can compose and receive the physical messages themselves. this provides more time for the microcontroller to carry out other func- tions such as calculating crypto algorithms, composing the logical messages and controlling other devices. due to that, a standard 4-/8-bit microcontroller without special periphery and clocked with the delivered clk output of about 4.5 mhz is sufficient to control the communica- tion link. this is especially valid for passive entry go and access control systems, where within less than 100 ms several communication responses with arbitration of the communication part- ner have to be handled. it is hence possible to design bi-directional rke and passive entry go systems with a fast challenge response crypto function and prevention against relay attacks. 3 4829c?rke?09/05 ATA5823/ata5824 figure 1-1. system block diagram 2. pin configuration figure 2-1. pinning qfn48 rf transceiver digital control logic c_interface power supply xto micro- controller ATA5823/ata5824 antenna 4 ... 8 matching/ rf switch nc nc nc rf_in nc 433_n868 nc r_pwr pwr_h rf_out nc nc rssi cs test3 sck sdi_tmdi sdo_tmdo clk irq pout vsint nc xtal2 nc nc rx_active n_pwr_on sck_pha sck_pol nc nc pwr_on rx_tx1 rx_tx2 cdem nc nc nc avcc vs2 vs1 setpwr test1 dvcc cs_pol test2 xtal1 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ATA5823/ata5824 4 4829c?rke?09/05 ATA5823/ata5824 table 2-1. pin description pin symbol function 1 nc not connected 2 nc not connected 3 nc not connected 4 rf_in rf input 5 nc not connected 6 433_n868 selects rf input/output frequency range 7 nc not connected 8 r_pwr resistor to adjust output power 9 pwr_h pin to select output power 10 rf_out rf output 11 nc not connected 12 nc not connected 13 nc not connected 14 nc not connected 15 nc not connected 16 avcc blocking of the analog voltage supply 17 vs2 power supply input for voltage range 4.4v to 5.6v 18 vs1 power supply input for voltage range 2.15v to 3.6v 19 setpwr internal programmable re sistor to adjust output power 20 test1 test input, at gnd during operation 21 dvcc blocking of the digital voltage supply 22 cs_pol select polarity of pin cs 23 test2 test input, at gnd during operation 24 xtal1 reference crystal 25 xtal2 reference crystal 26 nc not connected 27 vsint microcontroller interface supply voltage 28 pout programmable output 29 irq interrupt request 30 clk clock output to connect a microcontroller 31 sdo_tmdo serial data out/transparent mode data out 32 sdi_tmdi serial data in/transparent mode data in 33 sck serial clock 34 test3 test output open during operation 35 cs chip select for serial interface 36 rssi output of the rssi amplifier 37 cdem capacitor to adjust the lower cut-off frequency data filter 38 rx_tx2 has to be connected gnd 39 rx_tx1 switch pin to decouple lna in tx mode (rke mode) 40 pwr_on input to switch on the system (active high) 41 nc not connected 5 4829c?rke?09/05 ATA5823/ata5824 figure 2-2. block diagram 42 nc not connected 43 sck_pol polarity of the serial clock 44 sck_pha phase of the serial clock 45 n_pwr_on keyboard input (can also be us ed to switch on the system, active low) 46 rx_active indicates rx operation mode 47 nc not connected 48 nc not connected gnd ground/backplane (exposed die pad) table 2-1. pin description (continued) pin symbol function r_pwr rf_out rx_tx2 rf_in avcc gnd signal processing (mixer if-filter if-amplifier fsk/ask demodulator data filter data slicer) rf transceiver digital control logic dvcc pa_enable (ask) rx/tx frontend enable demod_out xtal1 xtal2 clk pout cs sck sdi_tmdi sdo_tmdo vs2 vs1 n_pwr_on pwr_on cdem setpwr rx_tx1 pwr_h rssi irq test3 c_interface vsint pa fract.-n- frequency synthesizer lna spi xto fref tx/rx - data buffer control register status register polling circuit bit-check logic synchronous logic (full duplex operation mode) rx_active test1 test2 freq 13 tx_data (fsk) power supply switches regulators wake-up reset reset rx/tx switch cs_pol sck_pol sck_pha 433_n868 6 4829c?rke?09/05 ATA5823/ata5824 3. typical key fob application for bi-directional rke figure 3-1. typical key fob application for bi-direction al rke with 5 dbm tx power, 433.92 mhz figure 3-1 shows a typical 433.92 mhz rke key fob application. the external components are 10 capacitors, 1 resistor, 2 inductors and a crystal. c 1 to c 3 are 68 nf voltage supply blocking capacitors. c 5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1 pf to 33 pf. l 1 is a matching inductor of about 5.6 nh to 56 nh. l 2 is a feed inductor of about 120 nh. a load capacitor of 9 pf for the crystal is inte- grated. r 1 is typically 22 k ? and sets the output power to about 5.5 dbm. the loop antenna?s quality factor is somewhat reduced by this application due to the quality factor of l 2 and the rx/tx switch. on the other hand, this lower quality factor is necessary to have a robust design with a bandwidth that is wide enough for produc tion tolerances. due to the single-ended and ground-referenced design, the loop antenna can be a free-form wire around the application as it is usually employed in rke unidirectional systems. the ATA5823/ata5824 provides sufficient isolation and robust pulling behavior of internal circuits from the supply voltage as well as an integrated vco inductor to allow this. since the efficiency of a loop antenna is proportional to the square of the surrounded area, it is beneficial to have a large loop around the application board with a lower quality factor to relax the tolerance specification of the rf matching components and to get a high antenna efficiency in spite of their lower quality factor. avcc rx_tx1 rx_tx2 dvcc vs2 vs1 vsint setpwr pwr_on pout xtal1 xtal2 clk test1 test3 n_pwr_on sck_pha sck_pol nc nc irq rssi cdem cs sck sdi_tmdi sdo_tmdo cs_pol nc rx_active rf_in nc nc r_pwr rf_out 433_n868 pwr_h nc nc nc nc nc nc nc test2 nc nc nc vcc vss avcc 20 mm 0.4 mm loop antenna microcontroller ATA5823/ata5824 litihum-cell c 1 c 9 c 8 c 10 c 5 c 11 c 6 c 3 + l 1 l 2 c 2 r 1 13.25311 mhz c 7 7 4829c?rke?09/05 ATA5823/ata5824 4. typical car application for bi-directional rke figure 4-1. typical car application for bi-directional rke with 10 dbm tx power, 433.92 mhz figure 4-1 shows a typical 433.92 mhz v cc = 4.4v to 5.25v rke car application. the external components are 11 capacitors, 1 resistor, 4 inductors, a saw filter and a crystal. c 1 , c 3 and c 4 are 68 nf voltage supply blocking capacitors. c 2 is a 2.2 f supply blocking capacitor for the internal voltage regulator. c 5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1 pf to 33 pf. l 2 to l 4 are matching inductors of about 5.6 nh to 56 nh. a load capacitor for the crystal of 9 pf is integrated. r 1 is typically 22 k ? and sets the output power at rf out to about 10 dbm . since a quarter wave or pcb antenna, which has high efficiency and wideband operation, is typically used here, it is recommended to use a saw filter to achieve high sensitivity in case of powerful out-of-band blockers. l 1 , c 10 and c 9 together form a low-pass filter, which is needed to filter out the harmonics in the transmitted signal to meet regulations. avcc rx_tx1 rx_tx2 dvcc vs2 vs1 vsint setpwr pwr_on pout xtal1 xtal2 clk test1 test3 n_pwr_on sck_pha sck_pol nc nc irq rssi cdem cs sck sdi_tmdi sdo_tmdo cs_pol nc rx_active rf_in nc nc r_pwr rf_out pwr_h nc nc nc nc nc nc nc test2 nc nc nc vcc vss avcc 20 mm 0.4 mm 50 ? connector microcontroller ATA5823/ata5824 c 1 c 2 c 9 c 8 c 10 c 5 c 7 c 6 c 3 l 2 c 4 r 1 13.25311 mhz rf out v cc = 4.4 v ... 5.25 v saw filter l 1 l 3 l 4 c 11 433_n868 8 4829c?rke?09/05 ATA5823/ata5824 5. typical key fob applicat ion for full-duplex peg figure 5-1. typical key fob application for full-duplex peg, 433.92 mhz figure 5-1 shows a typical 433.92 mhz peg key fob application. the external components are 10 capacitors, 1 resistor, 1 inductor and a crystal. c 1 to c 3 are 68 nf voltage supply blocking capacitors. c 7 is a 10 nf supply blocking capacitor. c 4 is a 15 nf fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. c 5 , c 6 , c 8 and c 9 are rf matching capacitors in the range of 1 pf to 33 pf. l 2 is a feed inductor of about 120 nh. c 10 is a 10 nf capacitor which is necessary to prevent that signals couple into the pin r_pwr, causing amplitude modulation of the output power and a spurious rise of the transmitted signal. r 1 and c 10 should be placed close to the r_pwr pin. a load capacitor of 9 pf for the crystal is integrated. r 1 is typically 22 k ? and setpwr is programmed to get an output power of ?7 dbm in full-duplex mode and 5 dbm in half-duplex mode. the quality factor of the loop antenna 1 is only reduced by the quality factor of l 2 , the tolerances of c 9 and c 8 are thus important. the qual- ity factor of the loop antenna 2 is reduced to half due to the loading with the input impedance of rf_in. with well designed loop antennas and the correct degree of overlapping, the isolation between rf_out and rf_in is about 28 db an d the coupled output power from rf_out to rf_in is about ?35 dbm. the decoupling of two loop antennas situated close to each other is due to the effect that the magnetic flux from the part of loop antenna 1 that does not overlap and that of the overlapping part has an opposite direction. depending on the relative position between the two antennas, a decoupling of 28 db is achievable. due to additional capacitive coupling between the loops the position of the components c 5 , c 6 and c 8 , c 9 are also important. the receive sensitivity in full-duplex mode is reduced from ?106 dbm without coupled rf-power at rf_in to ?96 dbm with ?35 dbm coupled rf power at rf_in. avcc rx_tx1 rx_tx2 dvcc vs2 vs1 vsint setpwr pwr_on pout xtal1 xtal2 clk test1 test3 n_pwr_on sck_pha sck_pol nc nc irq rssi cdem cs sck sdi_tmdi sdo_tmdo cs_pol nc rx_active rf_in nc nc r_pwr rf_out 433_n868 pwr_h nc nc nc nc nc nc nc test2 nc nc nc vcc vss avcc loop antenna 1 microcontroller ATA5823/ata5824 litihum-cell c 1 c 7 c 6 c 4 c 3 + l 2 c 2 r 1 13.25311 mhz loop antenna 2 c 5 20% overlap c 10 c 8 c 9 9 4829c?rke?09/05 ATA5823/ata5824 6. typical car application for full-duplex peg figure 6-1. typical car application for full-duplex peg, 433.92 mhz figure 6-1 shows a typical 433.92 mhz v cc = 4.4v to 5.25v peg car application. the external components are 11 capacitors, 1 resistor, 3 inductors, a saw filter and a crystal. c 1 , c 3 and c 4 are 68 nf voltage supply blocking capacitors. c 2 is a 2.2 f supply blocking capacitors for the internal voltage regulator. c5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. c 7 to c 10 are rf matching capacitors in the range of 1 pf to 33 pf. l 1 is a feed inductor of about 120 nh, l 2 and l 3 are matching inductors to match the rx-antenna to the saw and the saw to rf_in. a load capacitor of 9 pf for the crystal is integrated. c 11 is a 10 nf capacitor which is necessary to prevent that signals couple into the pin r_pwr, causing amplitude modulation of the output power and a spurious rise of the transmitted signal. r 1 and c 11 should be placed close to the r_pwr pin. r 1 is typically 22 k ? and setpwr is programmed to get an output power of 0 dbm in full-duplex mode and 5 dbm in half-duplex mode. the quality factor of the tx-loop antenna is only reduced by the quality factor of l 1 , the tolerances of c 9 and c 10 are thus important. since the 2 antennas are located at different places the isolation between rf_out and rf_in is about 45 db and the coupled output power from rf_out to rf_in is about ? 45 dbm. the receive sensitivity in full-duplex mode is reduced from ? 106 dbm without coupled rf power at rf_in to ? 102 dbm with ? 45 dbm coupled rf power at rf_in. the use of saw fil- ters in the full-duplex system is unsuitable due to the high group delay which desensitize the receiver. avcc rx_tx1 rx_tx2 dvcc vs2 vs1 vsint setpwr pwr_on pout xtal1 xtal2 clk test1 test3 n_pwr_on sck_pha sck_pol nc nc irq rssi cdem cs sck sdi_tmdi sdo_tmdo cs_pol nc rx_active rf_in nc nc r_pwr rf_out pwr_h nc nc nc nc nc nc nc test2 nc nc nc vcc v ss avcc 50 ? connector to rx antenna microcontroller ATA5823/ata5824 c 1 c 2 c 10 c 5 c 7 c 6 c 3 l 1 c 4 r 1 13.25311 mhz rfin v cc = 4.4 v ... 5.25 v saw filter l 3 l 2 c 8 433_n868 c 9 tx loop antenna (located in the control unit) c 11 10 4829c?rke?09/05 ATA5823/ata5824 7. rf transceiver in half-duplex mode according to figure 2-2 on page 5 , the rf transceiver consists of an lna (low-noise amplifier), pa (power amplifier), rx/tx switch, fractional-n frequency synthesizer and the signal process- ing part with mixer, if filter, if amplifier with analog rssi, fsk/ask demodulator, data filter and data slicer. in receive mode the lna pre-amplifies the receiv ed signal which is converted down to 226 khz intermediate frequency (if), filtered and amplified before it is fed into an fsk/ask demodulator, data filter and data slicer. the rssi (received signal strength indicator) signal and the raw dig- ital output signal of the demodulator are available at the pins rssi and on test3 (open drain output). the demodulated data signal demod_out is f ed into the digital control logic where it is evaluated and buffered as described in section ?digital control logic? on page 35 . in transmit mode the fractional-n frequency synthesizer generates the tx frequency which is fed into the pa. in ask mode the pa is modulated by the signal pa_ enable. in fsk mode the pa is enabled and the signal tx_data (fsk) modulates the fractional-n frequency synthesizer. the frequency deviation is digitally controlled a nd internally fixed to about 19.5 khz (see table 9-1 on page 30 for exact values). the transmit data can also be buffered as described in section ?digital control logic? on page 35 . a lock detector within the synthesizer ensures that the trans- mission will only start if the synthesizer is locked. in half-duplex mode the rx/tx switch can be used to combine the lna input and the pa output to a single antenna with a minimum of losses. in full-duplex mode more isolation between receive and transmit antenna is needed, therefore two antennas have to be used. transparent modes without buffering of rx and tx data are also available to allow protocols and coding schemes other than the internal supported manchester encoding, like pwm and pulse position coding. 7.1 low-if receiver the receive path consists of a fully integrated low-if receiver. it fulfills the sensitivity, blocking, selectivity, supply voltage and supply current specification needed to manufacture an automo- tive key fob for rke and peg systems without the use of a saw blocking filter (see figure 3-1 on page 6 and figure 5-1 on page 8 ). the receiver can be connected to the roof antenna in the car when using an additional blocking saw front-end filter as shown in figure 4-1 on page 7 . at 433.92 mhz the receiver has a typical system noise figure of 6.5 db, a system i1dbcp of ? 30 dbm and a system iip3 of ? 20 dbm. the signal path is linear for disturbers up to the i1dbcp and there is hence no agc or switching of the lna needed to achieve a better blocking perfor- mance. this receiver uses an if of about 226 khz (see table ?electrical characteristics? number 2.10 for exact values), the typical image rejection is 30 db and the typical 3 db system band- width is 220 khz (f if = 226 khz 110 khz, f lo_if = 116 khz and f hi_if = 336 khz). the demodulator needs a signal to noise ratio of 8 db for 20 kbaud manchester with 19.5 khz fre- quency deviation in fsk mode, thus, the result ing sensitivity at 433.92 mhz is typically ? 105.5 dbm. due to the low phase noise and spurious of the synthesizer in receive mode (1) together with the eighth order integrated if filter the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiving frequencies. note: 1. ?120 dbc/hz at 1 mhz and ?72 dbc at f xto at 433.92 mhz 11 4829c?rke?09/05 ATA5823/ata5824 a low-if architecture is also less sensitive to second-order intermodulation (iip2) than direct conversion receivers where every pulse or ampl itude modulated signal (especially the signals from tdma systems like gsm) demodulates to the receiving signal band at second-order non-linearities. 7.2 input matching at rf_in the measured input impedances as well as the val ues of a parallel equivalent circuit of these impedances can be seen in table 7-1 . the highest sensitivity is achieved with power matching of these impedances to the source impedance of 50 ? . the matching of the lna input to 50 ? was done with the circuit according to figure 7-1 and with the values of the matching elements given in table 7-2 . the reflection coefficients were always ? 10 db. note that value changes of c 1 and l 1 may be necessary to compensate individual board layout parasitics. the measured typical f sk and ask manchester code sensitivities with a bit error rate (ber) of 10 -3 are shown in table 7-3 on page 12 and table 7-4 on page 12 . these measurements were done with multilayer inductors having quality factors according to table 7-2 , resulting in estimated matching losses of 0.8 db at 315 mhz, 0.8 db at 433.92 mhz and 0.7 db at 868.3 mhz. these losses can be estimated when calculating the parallel equiva- lent resistance of the inductor with r loss = 2 f l q l and the matching loss with 10 log(1+r in_p /r loss ). with an ideal inductor, for example, the sensitivity at 433.92 mhz/fsk/20 kbaud/ 19.5 khz/manchester can be improved from ? 105.5 dbm to ? 106.7 dbm. the sensitivity also depends on the values in the registers of the control logic which examines the incoming data stream. the examination limits must be programmed in control registers 5 and 6. the measure- ments in table 7-3 and table 7-4 on page 12 are based on the values of registers 5 and 6 according to table 14-3 on page 60 . figure 7-1. input matching to 50 ? table 7-1. measured input impedances of the rf_in pin f rf /mhz z in (rf_in) r in_p //c in_p 315 (44-j233) ? 1278 ? //2.1 pf 433.92 (32-j169) ? 925 ? //2.1 pf 868.3 (21-j78) ? 311 ? //2.2 pf ATA5823/ata5824 rf_in 4 c 1 l 1 12 4829c?rke?09/05 ATA5823/ata5824 7.3 sensitivity versus supply voltag e, temperature and frequency offset to calculate the behavior of a tr ansmission system it is important to know the reduction of the sensitivity due to several influences. the most important are frequency offset due to crystal oscillator (xto) and crystal frequency (xtal) errors, temperature and supply voltage depen- dency of the noise figure and if filter bandwidth of the receiver. figure 7-2 shows the typical sensitivity at 433.92 mhz/fsk/20 kbaud/19.5 khz/manchester versus the frequency offset between transmitter and receiver at t amb = ? 40c, +25c and +105c and supply voltage v s = v s1 = v s2 = 2.15v, 3.0v and 3.6v. figure 7-2. measured sensitivity 433.92 mhz/fsk/20 kbaud/19.5 khz/manchester versus frequency offset, temper- ature and supply voltage table 7-2. input matching to 50 ? f rf /mhz c 1 /pf l 1 /nh q l1 315 2.4 47 65 433.92 1.8 27 67 868.3 1.2 6.8 50 table 7-3. measured typical sensitivity 433.92 mhz, fsk, 19.5 khz, manchester, ber = 10 -3 rf frequency br_range_0 1.0 kbaud br_range_0 2.4 kbaud br_range_1 5.0 kbaud br_range_2 10 kbaud br_range_3 20 kbaud 315 mhz ?109.5 dbm ?110.0 dbm ?109.0 dbm ?107.5 dbm ?106.5 dbm 433.92 mhz ?108.5 dbm ?109.0 dbm ?108.0 dbm ?106.5 dbm ?105.5 dbm 868.3 mhz ?105.5 dbm ?106.5 dbm ?105.5 dbm ?103.5 dbm ?103.0 dbm table 7-4. measured typical sensitiv ity 433.92 mhz, 100% ask, manchester, ber = 10 -3 rf frequency br_range_0 1.0 kbaud br_range_0 2.4 kbaud br_range_1 5.0 kbaud br_range_2 10 kbaud 315 mhz ?117.0 dbm ?117.0 dbm ?114.5 dbm ?112.5 dbm 433.92 mhz ?116.0 dbm ?116.0 dbm ?113.5 dbm ?111.5 dbm 868.3 mhz ?113.0 dbm ?113.0 dbm ?111.5 dbm ?109.0 dbm -102.0 -100.0 -99.0 -98.0 -97.0 -96.0 -95.0 sensitivity/dbm -109.0 -108.0 -106.0 -104.0 -103.0 -101.0 frequency offset/khz -105.0 -107.0 -110.0 0 -100 -80 -60 -40 -20 20 40 60 80 100 v s = 2.15 v t amb = -40c v s = 3.0 v t amb = -40c v s = 3.6 v t amb = -40c v s = 2.15 v t amb = 25c v s = 3.0 v t amb = 25c v s = 3.6 v t amb = 25c v s = 2.15 v t amb = 105c v s = 3.0 v t amb = 105c v s = 3.6 v t amb = 105c 13 4829c?rke?09/05 ATA5823/ata5824 as can be seen in figure 7-2 on page 12 the supply voltage has almost no influence on the sen- sitivity. the temperature has an influence of about +1.5/ ? 0.7 db and a frequency offset of 85 khz also influences by about 1 db. all thes e influences, combined with the sensitivity of a typical ic ( ? 105.5dbm), are then within a range of ? 102.5 dbm and ? 107 dbm overtemperature, supply voltage and frequency offset. the integrated if filter has an additional production toler- ance of 10 khz, hence, a frequency offset between the receiver and the transmitter of 75 khz can be accepted for xtal and xto tolerances. note: for the demodulator used in the ATA5823/at a5824, the tolerable frequency offset does not change with the data frequency, hence, the value of 75 khz is valid for 1 kbaud to 20 kbaud. this small sensitivity change over supply voltage, frequency offset and temperature is very unusual in such a receiver. it is achieved by an internal, very fast and automatic frequency cor- rection in the fsk demodulator after the if filter, which leads to a higher system margin. this frequency correction tracks the input frequency very quickly, if however, the input frequency makes a larger step (e.g., if the system changes between different communication partners), the receiver has to be restarted. this can be done by switching back to idle mode and then again to rx mode. for that purpose, an automatic mode is also available. this automatic mode switches to idle mode and back into rx mode every time a bit error occurs (see section ?digital control logic? on page 35 ). 7.4 frequency accuracy of the crystals in bi-directional rke/peg the xto is an amplitude regulated pierce type oscillator with integrated load ca pacitors. the ini- tial tolerances (due to the frequency tolerance of the xtal, the integrated capacitors on xtal1, xtal2 and the xto?s initial transconductance gm) can be compensated to a value within 0.5 ppm by measuring the clk output frequency and tuning of f rf by programming the control registers 2 and 3 (see table 12-7 on page 38 and table 12-10 on page 39 ). the xto then has a remaining influence of less than 2 ppm overtemperature and supply voltage due to the band- gap controlled gm of the xto. thus only 2.5 ppm add to the frequency stability of the used crystals overtemperature and aging. the needed frequency stability of the used crystals overtemperature and aging is hence 75 khz/433.92 mhz ? 2 2.5 ppm = 167.84 ppm for 433.92 mhz and 75 khz/868.3 mhz ? 2 2.5 ppm = 81.4 ppm for 868.3 mhz. thus, the used crystals in receiver and transmitter each need to be better than 83.9 ppm for 433.92 mhz and 40.7 ppm for 868.3 mhz. 7.5 frequency accuracy of the crystals in a combined rke/p eg and tpm system in a tire pressure measurement system working at 433.92 mhz and using a tpm transmitter ata5757 and a transceiver ata5824 as a receiver, the higher frequency tolerances and the tol- erance of the frequency deviation of this transmitter has to be considered. in the tpm transmitter the crystal has an frequency error overtemperature ? 40c to +125c, aging and tolerance of 80 ppm (34.7 khz at 433.92 mhz). the tolerances of the xto, the capacitors used for fsk-modulation and the stra y capacitors, causing an additional frequency error of 30 ppm (13 khz at 433.92 mhz). the frequency deviation of such a transmitter varies between 16 khz and 24 khz, since a higher freq uency deviation is equivalent to an frequency error, this has to be considered as an additional 24 khz ? 19.5 khz = 4.5khz frequency tol- erance. all tolerances added, these transmitters have a worst case frequency offset of 52.2 khz. 14 4829c?rke?09/05 ATA5823/ata5824 for the transceiver in the car a tolerance of 75 khz ? 52.2 khz = 22.8 khz (52.5 ppm) remains. the needed frequency stability of the used crystals overtemperature and aging is 52.5 ppm ? 2.5 ppm = 50 ppm. the aging of such a crystal is 10 ppm leaving reasonable 40 ppm for the temperature dependency of the crystal frequency in the car. since the transceiver in the car is able to rec eive these tpm transmitter signals with high fre- quency offsets, the component specificat ion in the key can be largely relaxed. this system calculation is based on worst case tolerances of all the components, this leads in practice to a system with margin. for a 315 mhz tpm system using a tpm transmitter ata5756 and a transceiver ATA5823 as receiver the same calculation must be done, but since the rf frequency is lower, every ppm of crystal tolerances results in less frequency offs et and either the system can have higher toler- ances or a higher margin there. for 868 mhz it is not possible to use the transceiver ata5824 in a combined rke/peg and tpm system since all the tolerances double because of the higher rf frequency. 7.6 rx supply current versus temperature and supply voltage table 7-5 shows the typical supply current at 433.92 mhz of the transceiver in rx mode versus supply voltage and temperature with v s = v s1 = v s2 . as can be seen the supply current at v s = 2.15v and t amb = ? 40c is less than at v s = 3v/t amb = 25 which helps to enlarge the bat- tery lifetime within a key fob application because this is also the operation point where a lithium cell has the worst performance. the typical supply current at 315 mhz or 868.3 mhz in rx mode is about the same as for 433.92 mhz. 7.7 blocking, selectivity as can be seen in figure 7-3 , figure 7-4 and figure 7-5 on page 15 , the receiver can receive signals 3 db higher than the sensitivity le vel in presence of large blockers of ? 44.5 dbm/-36.0 dbm with small frequency offsets of 1 / 10 mhz. figure 7-3 and figure 7-4 on page 15 shows the close-in and narrow-band blocking and figure 7-5 on page 15 the wide-band blocking characteristic. th e measurements were done with a use- ful signal of 433.92 mhz/fsk/20 kbaud/19.5 khz/manchester with a level of ? 105.5 dbm + 3 db = ? 102.5 dbm which is 3 db above the sensitivity level. the figures show by how much a continuous wave signal can be larger than ? 102.5 dbm until the ber is higher than 10 -3 . the measurements were done at the 50 ? input according to figure 7-1 on page 11 . at 1 mhz, for example, the blocker can be 58 dbc higher than ? 102.5 dbm which is ? 102.5 dbm +58 dbc = ? 44.5 dbm. these blocking figures, together with the good intermodulation perfor- mance, avoid the additional need of a saw filter in the key fob application. table 7-5. measured 433.92 mhz receive supply current in fsk mode v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c 8.2 ma 8.8 ma 9.2 ma t amb = 25c 9.7 ma 10.3 ma 10.8 ma t amb = 105c 11.2 ma 11.9 ma 12.4 ma 15 4829c?rke?09/05 ATA5823/ata5824 figure 7-3. close in 3 db blocking characteristic and image response at 433.92 mhz figure 7-4. narrow band 3 db blocking characteristic at 433.92 mhz figure 7-5. wide band 3 db blocking characteristic at 433.92 mhz -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 -1.0 -0.8 -0.6 -0.4 -0.2 -0.0 0.2 0.4 0.6 0.8 1.0 distance of interfering to receiving signal [mhz] blocking [dbc] -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 distance of interfering to receiving signal [mhz] blocking [dbc] -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 distance of interfering to receiving signal [mhz] blocking [dbc] 16 4829c?rke?09/05 ATA5823/ata5824 table 7-6 shows the blocking performance measured relative to ? 102.5 dbm for some frequen- cies. note that sometimes the blocking is measured relative to the sensitivity level ? 105.5 dbm (denoted dbs) instead of the carrier ? 102.5 dbm (denoted dbc). the ATA5823/ata5824 can also receive fsk and ask modulated signals if they are much higher than the i1dbcp. it can typically receive us eful signals at +10 dbm. this is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is 115.5 db for 433.92 mhz/fsk/20kbaud/19.5 khz/ manchester. this value is useful if two transceivers have to communicate and are very close to each other. in a keyless entry system there is another blocking characteristic that has to be considered. a keyless entry system has a typical service range of about 30 m with a receiver sensitivity of about ? 106 dbm to ? 109 dbm. in some cases, large blockers limit this service range, and it is important to know how large this blockers can be until the system doesn?t work anymore and the user has to use its key. with a recommended sensitivity of about ? 85 dbm, the system works just around the car. figure 7-6 and figure 7-7 on page 17 show the blocking performance in this important case with a useful signal of ? 85dbm 433.92 mhz/fsk/20kbaud/19.5 khz/ manchester. as can be seen the system works even with blo ckers above the compression point. this is due to a wide bandwidth automatic gain control that begins to work if blockers above the compres- sion point are at the antenna input and increasing the current in the lna/mixer to get a better compression point needed to handle these large blockers. figure 7-6. 2.5 mhz blocking characteristic for ? 85 dbm useful signal at 433.92 mhz table 7-6. blocking 3 db above sensitivity level with ber < 10 -3 frequency offset blocker level blocking +0.75 mhz ?47.5 dbm 55.0 dbc/58.0 dbs ?0.75 mhz ?47.5 dbm 55.0 dbc/58.0 dbs +1.0 mhz ?44.5 dbm 58.0 dbc/61.0 dbs ?1.0 mhz ?44.5 dbm 58.0 dbc/61.0 dbs +1.5 mhz ?42.0 dbm 60.5 dbc/63.5 dbs ?1.5 mhz ?42.0 dbm 60.5 dbc/63.5 dbs +10 mhz ?35.5 dbm 67.0 dbc/70.0 dbs ?10 mhz ?35.5 dbm 67.0 dbc/70.0 dbs -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 distance of interfering to receiving signal [mhz] blocker level [dbm] 17 4829c?rke?09/05 ATA5823/ata5824 figure 7-7. 50 mhz blocking characteristic for ? 85 dbm useful signal at 433.92 mhz this high blocking performance makes it even possible for some applications using quarter wave whip antennas to use a simple lc band-pass f ilter instead of a saw filter in the receiver. when designing such a lc filter, take into account that the 3 db blocking at 433.92 mhz/2 = 216.96 mhz is 42 dbc and at 433.92 mhz/3 = 144.64 mhz is 47 dbc and at 2 (433.92 mhz + 226 khz) + ? 226 khz = 868.066 mhz/868.518 mhz is 50 dbc. and espe- cially that at 3 (433.92 mhz + 226 khz)+226 khz = 1302.664 mhz the receiver has a second lo harmonic receiving frequency with only 17 dbc blocking. 7.8 inband disturbers, data filter , quasi-peak detector, data slicer if a disturbing signal falls into the received band, or a blocker is not a continuous wave, the per- formance of a receiver strongly depends on the circuits after the if filter. hence the demodulator, data filter and data slicer are important in that case. the data filter of the ATA5823/ata5824 implies a quasi-peak detector. this results in a good suppression of above mentioned disturbers and exhibits a good carrier to noise performance. the required ratio of useful signal to disturbing signal, at a ber of 10 -3 is less than 12 db in ask mode and less than 3 db (br_range_0 ... br_range_2) and 6 db (br_range_3) in fsk mode. due to the many different possible waveforms these numbers are measured for signal as well as for disturbers with peak amplitude values. note that these values are worst case values and are valid for any type of modulation and modulating frequency of the disturbing signal as well as the receiving signal. for many combinations , lower carrier to disturbing signal ratios are needed. 7.9 test3 output the internal raw output signal of the demodulator demod_out is available at pin test3. test3 is an open drain output and must be connected to a pull-up resistor if it is used (typically 100 k ? ), otherwise no signal is present at that pin. this signal is mainly used for debugging purposes dur- ing the setup of a new application, since the received data signal can be seen there without any digital processing. -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 distance of interfering to receiving signal [mhz] blocker level [dbm] 18 4829c?rke?09/05 ATA5823/ata5824 7.10 rssi output the output voltage of the pin rssi is an analog voltage, proportional to the input power level. using the rssi output signal, the signal strength of different transmitters can be distinguished. the usable dynamic range of the rssi amplifier is 70 db, the input power range p rfin is ? 115 dbm to ? 45 dbm and the gain is 8 mv/db. figure 7-8 on page 18 shows the rssi charac- teristic of a typical device at 433.92 mhz with v s1 = v s2 = 2.15v to 3.6v and t amb = ? 40c to +105c with a matched input according to table 7-2 on page 12 and figure 7-1 on page 11 . at 868.3 mhz about 2.7 db more signal level and at 315 mhz about 1 db less signal level is needed for the same rssi results. figure 7-8. typical rssi characteristic at 433.92 mhz versus temperature and supply voltage 7.11 frequency synthesize r and channel selection the synthesizer is a fully integrated fractional-n des ign with internal loop filters for receive and transmit mode. the xto frequency f xto is the reference frequency fref for the synthesizer. the bits fr0 to fr12 in control registers 2 and 3 (see table 12-7 on page 38 and table 12-10 on page 39 ) are used to adjust the deviation of f xto . in half-duplex transmit mode, at 433.92 mhz, the carrier has a phase noise of ? 111 dbc/hz at 1 mhz and spurious at fref of ? 70 dbc with a high pll loop bandwidth allowing the direct modulation of the carrier with 20 kbaud manchester data. due to the closed loop modulation, any spurious caused by this modulation are effectively filtered out as can be seen in figure 7-11 on page 20 . in rx mode the synthesizer has a phase noise of ? 120 dbc/hz at 1 mhz and spurious of ? 72 dbc. the initial tolerances of the crys tal oscillator due to cr ystal frequency tolera nces, internal capac- itor tolerances and the parasitics of the board have to be compensated at manufacturing setup with control registers 2 and 3 as can be seen in table 9-1 on page 30 . the other control words for the synthesizer needed for ask, fsk and recei ve/transmit switching are calculated inter- nally. the rf (radio frequency) resolution is equal to the xto frequency divided by 16384 which is 777.1 hz at 315.0 mhz, 808.9 hz at 433.92 mhz and 818.59 hz at 868.3 mhz. the frequency control word freq in control registers 2 and 3 can be programmed in the range of 1000 to 6900, hence every frequency within the 433 mhz and 868 mhz ism bands can be programmed as receive and as transmit frequency and the position of channels within these ism bands can be chosen arbitrarily (see table 9-1 on page 30 ). 400 500 600 700 800 900 1000 1100 -120 -110 -100 -90 -80 -70 -60 -50 -40 p rf_in (dbm) v rssi (mv) max. min. typ. 19 4829c?rke?09/05 ATA5823/ata5824 care must be taken regarding the harmonics of the clk output signal as well as to the harmon- ics produced by a microprocessor clocked with it, since these harmonics can disturb the reception of signals. in a single channel system using freq = 3803 to 4053 ensures that har- monics of this signal, do not disturb the receive mode. 7.12 fsk/ask transmission due to the fast modulation capability of the synthesizer and the high resolution, the carrier can be internally fsk modulated which simplifies the application of the transceiver. the deviation of the transmitted signal is 24 di gital frequency steps of the synthesizer which is equal to 18.65 khz for 315 mhz, 19.41 khz for 433.92 mhz and 19.64 khz for 868.3 mhz. due to closed loop modulation with pll filtering, the modulated spectrum is very clean, meeting etsi and cept regulations when using a simple lc filter for the power amplifier harmonics as it is shown in figure 4-1 . in ask mode the frequen cy is internally connecte d to the center of the fsk transmission and the power amplifier is switched on and off to perform the modulation. figure 7-9 to figure 7-11 on page 20 show the spectrum of the fsk modulation with pseudo-random data with 20 kbaud/19.41 khz/manchester and 5 dbm output power. figure 7-9. fsk-modulated tx spectrum (433.92 mhz/20 kbaud/ 19.41 khz/manchester code) ref 10 dbm atten 20 db samp log 10 db/ vavg 50 w1 s2 s3 fc center 433.92 mhz res bw 100 khz vbw 100 khz span 30 mhz sweep 7.5 ms (401 pts) 20 4829c?rke?09/05 ATA5823/ata5824 figure 7-10. unmodulated tx spectrum 433.92 mhz - 19.41 khz (f fsk_l ) figure 7-11. fsk-modulated tx spectrum (433.92 mhz/20 kbaud/19.41 khz/manchester code) ref 10 dbm atten 20 db samp log 10 db/ vavg 50 w1 s2 s3 fc center 433.92 mhz res bw 10 khz vbw 10 khz span 1 mhz sweep 27.5 ms (401 pts) ref 10 dbm atten 20 db samp log 10 db/ vavg 50 w1 s2 s3 fc center 433.92 mhz res bw 10 khz vbw 10 khz span 1 mhz sweep 27.5 ms (401 pts) 21 4829c?rke?09/05 ATA5823/ata5824 7.13 output power setting an d pa matching at rf_out the power amplifier (pa) is a single-ended open coll ector stage which deli vers a current pulse which is nearly independent of supply voltage, temperature and tolerances due to band-gap sta- bilization. resistor r 1 (see figure 7-12 on page 22 ) sets a reference current which controls the current in the pa. a higher resistor value resul ts in a lower reference current, a lower output power and a lower current consumption of the pa. the usable range of r 1 is 15 k ? to 56 k ? . the pwr_h pin switches the output power range between about 0 dbm to 5 dbm (pwr_h = gnd) and 5 dbm to 10 dbm (pwr_h = avcc) by multip lying this reference current with a factor 1 (pwr_h = gnd) and 2.5 (pwr_h = avcc) which corresponds to about 5 db more output power. if the pa is switched off in tx mode, the current consumption without output stage and with v s1 = v s2 = 3v, t amb = 25c is typically 6.5 ma for 868.3 mhz and 6.95 ma for 315 mhz and 433.92 mhz. the maximum output power is achieved with optimum load resistances r lopt according to table 7-7 on page 22 . the compensation of the 1.0 pf output capacitance of the rf_out pin will be achieved by absorbing it into the matching network, consisting of l 1 , c 1 , c 3 as shown in figure 7-12 on page 22 . there must be also a low resistive dc path to avcc to deliver the dc current of the power amplifier's last stage. the matching of the pa output was done with the circuit according to figure 7-12 on page 22 with the values in table 7-7 . note that value changes of these elements may be necessary to compensate individual board layout parasitics. example: according to table 7-7 on page 22 , with a frequency of 433.92 mhz and output power of 11 dbm, the overall current consumption is typically 17.8 ma. hence the pa needs 17.8 ma - 6.95 ma = 10.85 ma in this mo de which corresponds to an overall power amplifier efficiency of the pa of (10 (11dbm/10) 1 mw)/(3v 10.85 ma) 100% = 38.6% in this case. using a higher resistor in this example of r1 = 1.091 22 k ? = 24 k ? results in 9.1% less cur- rent in the pa of 10.85 ma/1.091 = 9.95 ma and 10 log(1.091) = 0.38 db less output power if using a new load resistance of 300 ? 1.091 = 327 ? . the resulting output power is then 11 dbm ? 0.38 db = 10.6 dbm and the overall current consumption is 6.95 ma + 9.95 ma = 16.9 ma. the values of table 7-7 on page 22 were measured with standard multi-layer chip inductors with quality factors q according to table 7-7 on page 22 . looking to the 433.92 mhz/11 dbm case with the quality factor of q l1 = 43 the loss in this induc- tor l 1 is estimated with the parallel equivalent resistance of the inductor r loss = 2 f l1 q l1 and the matching loss with 10 log (1 + r lopt /r loss ) which is equal to 0.32 db losses in this inductor. taking this into account the pa efficiency is then 42% instead of 38.6%. be aware that the high power mode (pwr_h = avcc) can only be used with a supply voltage higher than 2.7v, whereas the low power mode (pwr_h = gnd) can be used down to 2.15v as can be seen in the section ?electrical characteristics: general? on page 72 . the supply blocking capacitor c 2 (10 nf) in figure 7-12 on page 22 has to be placed close to the matching network because of the rf current flowing through it. 22 4829c?rke?09/05 ATA5823/ata5824 an internal programmable resistor setpwr is programmable with the control register 8, described in table 12-25 on page 43 . it can be used in conjunction with an external resistor to adjust the output power by connection it like in the application figure 5-1 on page 8 or figure 6-1 on page 9 . to do that the output power should be adjusted with an external resistor about 50% lower than needed for the target output power and reduced with the programmable resistor dur- ing production test until the target power is as close as possible to the target. for example, if using 433.92 mhz at 5 dbm, a resistor of 12k instead of 24k is used and values of pwset between 25 and 29 can be used to achieve an ou tput power within 5 dbm 0.5 db over produc- tion. in full-duplex mode this internal resistor is used to reduce the output power for full-duplex operation versus the power in half-duplex operation. note that this resistor is temperature stable but has tolerances of 20% and introduces, therefore, additional output power tolerances, it is recommended to adjust output power during the production test if using the setpwr resistor. figure 7-12. power setting and output matching ata5820/ata5821 rf_out 10 c 1 l 1 rf out avcc c 2 c 3 r_pwr pwr_h r 1 vpwr_h 8 9 table 7-7. measured output power and current consumption with v s1 = v s2 = 3v, t amb = 25c frequency (mhz) tx current (ma) output power (dbm) r1 (k ? ) vpwr_h r lopt ( ? ) l 1 (nh) q l1 c 1 (pf) c 3 (pf) 315 8.5 0.4 56 0 2500 82 28 1.5 0 315 10.5 5.7 27 0 920 68 32 2.2 0 315 16.7 10.5 27 avcc 350 56 35 3.9 0 433.92 8.6 0.1 56 0 2300 56 40 0.75 0 433.92 11.2 6.2 22 0 890 47 38 1.5 0 433.92 17.8 11 22 avcc 300 33 43 2.7 0 868.3 9.3 ?0.3 33 0 1170 12 58 1.0 3.3 868.3 11.5 5.4 15 0 471 15 54 1.0 0 868.3 16.3 9.5 22 avcc 245 10 57 1.5 0 23 4829c?rke?09/05 ATA5823/ata5824 7.14 output power and tx supply curr ent versus supply voltage and temperature table 7-8 shows the measurement of the output power for a typical device with v s1 = v s2 = v s in the 433.92 mhz and 6.2 dbm case versus temp erature and supply voltage measured according to figure 7-12 on page 22 with components according to table 7-7 on page 22 . as opposed to the receiver sensitivity the supply voltage has here the major impact on output power variations because of the large signal behavior of a power am plifier. thus a 5v system using the internal voltage regulator shows much less variation t han a 2.15v to 3.6v battery system because the avcc supply voltage is 3.25v 0.25v for a 5v system. the reason is that the amplitude at the output rf_out with optimum load resistance is avcc ? 0.4v and the power is proportional to (avcc ? 0.4v) 2 if the load impedance is not changed. this means that the theoretical output power reduction if reducing the supply voltage from 3.0v to 2.15v is 10 log ((3v ? 0.4v) 2 /(2.15v ? 0.4v) 2 ) = 3.4 db. table 7-8 shows that princi- ple behavior in the measurements. this is not the same case for higher voltages, since here, increasing the supply voltage from 3v to 3.6v should theoretical increase the power by 1.8 db, but only 0.9 db in the measurements shows that the amplitude does not increase with the supply voltage because the load impedance is optimized for 3v and the output amplitude stays more constant because of the current source nature of the output. . table 7-9 shows the relative changes of the output power of a typical device compared to 3.0v/25c. as can be seen, a temperature change to ? 40c as well as to +105c reduces the power by less than 1 db due to the band-gap regulated output current. measurements of all the cases in table 7-7 on page 22 overtemperature and supply voltage have shown about the same relative behavior as shown in table 7-9 . table 7-8. measured output power and supply current at 433.92 mhz, pwr_h = gnd v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c 9.25 ma 3.2 dbm 10.19 ma 5.5 dbm 10.78 ma 6.2 dbm t amb = +25c 10.2 ma 3.4 dbm 11.19 ma 6.2 dbm 11.79 ma 7.1 dbm t amb = +105c 10.9 ma 3.0 dbm 12.02 ma 5.4 dbm 12.73 ma 6.3 dbm table 7-9. measurements of typical output power relative to 3 v/25c v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c ?3.0 db ?0.7 db 0 db t amb = +25c ?2.8 db 0 db +0.9 db t amb = +105c ?3.2 db ?0.8 db +0.1 db 24 4829c?rke?09/05 ATA5823/ata5824 7.15 rx/tx switch the rx/tx switch decouples the lna from the pa in tx mode, and directs the received power to the lna in rx mode. to do this, it has a low impedance to gnd in tx mode and a high impedance to gnd in rx mode. the pin 38 (rx_tx2) must always be connected to gnd in the application. to design a proper rx/tx decoupling a linear simulation tool for radio frequency design together with the measured device impedances of table 7-1 on page 11 , table 7-7 on page 22 , table 7-10 on page 24 and table 7-11 on page 25 should be used. the exact element values have to be found on board. figure 7-13 on page 24 shows an approximate equivalent cir- cuit of the switch. the principal switching operation is described here according to the application of figure 3-1 on page 6 . the application of figure 4-1 on page 7 works similarly. . figure 7-13. equivalent circuit of the switch 7.16 matching network in tx mode in tx mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than /4 is approximately switched in parallel to the capacitor c 9 to gnd. the antenna connection between c 8 and c 9 has an impedance of about 50 ? looking from the transmission line into the loop antenna with pin rf_out, l 2 , c 10 , c 8 and c 9 connected (using a c 9 without the added 7.6 pf capacitor as discussed later). the transm ission line can be approximated with a 16 nh inductor in series with a 1.5 ? resistor, the closed switch can be approximated according to table 7-10 with the series connection of 1.6 nh and 5 ? in this mode. to have a parallel resonant high impedance circuit with little rf power going into it looking, from the loop antenna into the trans- mission line a capacitor of about 7.6 pf to gnd is needed at the beginning of the transmission line (this capacitor is later absorbed into c 9 , which is then higher as needed for 50 ? transforma- tion). to keep the 50 ? impedance in rx mode at the end of this transmission line c 7 has to be also about 7.6 pf. this reduces the tx power by about 0.5 db at 433.92 mhz compared to the case where the lna path is completely disconnected. table 7-10. impedance of the rx/tx switch rx_tx2 shorted to gnd frequency z(rx_tx1) tx mode z(rx_tx1) rx mode 315 mhz (4.8 + j3.2) ? (11.3 ? j214) ? 433.92 mhz (4.5 + j4.3) ? (10.3 ? j153) ? 868.3 mhz (5 + j9) ? (8.9 ? j73) ? 1.6 nh rx_tx1 2.5 pf 11 ? tx 5 ? 25 4829c?rke?09/05 ATA5823/ata5824 7.17 matching network in rx mode in rx mode the rf_out pin has a high impedance of about 7 k ? in parallel with 1.0 pf at 433.92 mhz as can be seen in table 7-11 on page 25 . this together with the losses of the inductor l 2 with 120 nh and q l2 = 25 gives about 3.7 k ? loss impedance at rf_out. since the optimum load impedance in tx mode for the power amplifier at rf_out is 890 ? the loss asso- ciated with the inductor l 2 and the rf_out pin can be estimated to be 10 log(1 + 890/3700) = 0.95 db compared to the optimum matched loop antenna without l 2 and rf_out. the switch represents, in this mode at 433.92 mhz, about an inductor of 1.6 nh in series with the parallel connection of 2.5 pf and 2.0 k ? . since the impedance level at pin rx_tx1 in rx mode is about 50 ? there is only a negligible damping of the received signal by about 0.1 db. when matching the lna to the loop antenna the transmission line and the 7.6 pf part of c 9 has to be taken into account when choosing the values of c 11 and l 1 so that the impedance seen from the loop antenna into the transmission line with the 7.6 pf capacitor con- nected is 50 ? . since the loop antenna in rx mode is loaded by the lna input impedance the loaded q of the loop antenna is lowered by about a factor of 2 in rx mode hence the antenna bandwidth is higher than in tx mode. . note that if matching to 50 ? , like in figure 4-1 on page 7 , a high q wire wound inductor with a q > 70 should be used for l 2 to minimize its contribution to rx losses which will otherwise be dominant. the rx and tx losses will be in the range of 1.0 db there. 8. rf transceiver in full-duplex mode the full-duplex mode of the ATA5823/ata5824 is intended to be used for the purpose of secu- rity against a so called relay attack in passive entry systems. a property of such a passive entry system is that the user has not to push a key fob button like in a keyless entry system. if the user approaches to the door of the car it will wake up the key (in most cases with a low frequency 125 khz signal) and the communication between the key and the car starts without interaction of the user and afterwards the door opens. due to this new feature of the s ystem there is a new possibility of entering a car without permis- sion. one can trigger this communication, take the 125 khz signal from the car, remodulate it on another carrier and transmit it over a much longer distance than intended by the system. than receive this signal and remodulate it onto the 125 khz carrier and retransmit this signal close to the user having the key fob with permission for the car. such a system is called an rf-relay and therefore this kind of attack is called relay attack. the high frequency signals of the ATA5823/ata5824 could be treated the same way if only a half-duplex mode is used within a passive entry system. if using half-duplex rf transc eivers, the attacker can switch the direction of the relay with a transmit power detector. table 7-11. impedance rf_out pin in rx mode frequency z(rf_out)rx r p //c p 315 mhz 36 ? ? j 502 ? 7 k ?/ / 1.0 pf 433.92 mhz 19 ? ? j 366 ? 7 k ?/ / 1.0 pf 868.3 mhz 2.8 ? ? j 141 ? 7 k ?/ / 1.3 pf 26 4829c?rke?09/05 ATA5823/ata5824 to prevent that the ATA5823/ata5824 receives and transmit its rf-signals on the same fre- quency and at the same time. since the attacker has then to receive and transmit rf signals at the same frequency and time it w ill be much more difficult to built the hardware for this kind of attack, since its own transmitted output power couples back to its receiver. this mode works as follows: both transceivers transmit fsk with a modulation deviation of half the if (a frequency deviation of about 113 khz), switches the image rejection in the receive path off and uses the transmit frequency as local oscillator for the receiver. if both transceivers send fsk-low or both send fsk-high, the resulting if is close to zero and is filtered out by the if-filter. both receivers receive than a low-signal by us ing the ask demodulator as receiver . if the transce ivers send dif- ferent symbols e.g. fsk-low/fsk-high or fsk-high/fsk-low the resulting if is close to 226 khz and the ask demodulator receives a high-signal. since the transceivers are synchronized at the beginning of the data transfer, they can calculat e the transmitted data of the other transceiver from their own transmitted data and the data received from the ask demodulator. to use that mode, the received power from the transmitter side of a transceiver should not cou- ple with a to high magnitude to its lna ot herwise the receive path will be desensitized. therefore, two different antennas for transmit and receive are used with good decoupling (see figure 5-1 on page 8 and figure 6-1 on page 9 ). since defined packets are transmitted in fd-mode and the critical point in the transmission is the synchronization and not the data transfer, the sens itivity in fd-mode is def ined for packets with 8 bytes of useful data (usually the response from a crypto-challenge response transmission) and for a p acket e rror r ate per of 5%. for the full-duplex mode the data rate is fixed to 5 kbaud the sensitivity of the receiver in full-duplex mode is dependant on the absolute power value and the phase of the power coupled from the pa to the lna. due to the phase dependency, three values are given in the table 8-1 , the first is the typical and the second and third one shows the sensitivity variation. the ic internal decoupling of the rf in from rf out with a power amplifier load impedance opti- mized for +5dbm is 65 db on a well designed pc b, hence the coupling is mainly due to the cross-coupling of the antennas. table 8-1. typical full-duplex sensitivity dependent on the parasitic received power and coupling phase from the pa 433.92 mhz/full-duplex mode/5 kbaud per = 5% at 3v, 25c power from rf out at rf in /dbm typical sensitivity/dbm s ensitivity variation/dbm ?30 ?91 ?88.5/?92.5 ?35 ?96 ?93.5/?97.5 ?40 ?100 ?97.5/?101.5 ?45 ?103 ?100.5/?104.5 ?50 ?104 ?101.5/?105.5 27 4829c?rke?09/05 ATA5823/ata5824 9. xto the xto is an amplitude regulated pierce oscillator type with integrated load capacitances (2 18 pf with a tolerance of 17%) hence c lmin = 7.4 pf and c lmax = 10.6 pf. the xto oscil- lation frequency f xto is the reference frequency fref for the fractional-n synthesizer. when designing the system in terms of receiving and transmitting frequency offset the accuracy of the crystal and xto have to be considered. the synthesizer can adjust the local oscillator frequency for the initia l frequency error in f xto . this is done at nominal supply voltage and temperature with the control registers 2 and 3 (see table 12-7 on page 38 and table 12-10 on page 39 ). the remaining local oscillator tolerance at nominal supply voltage and temperature is then < 0.5 ppm. the xto?s gm has very low influ- ence of less than 2 ppm on the frequency at nominal supply voltage and temperature. in a single channel system less than 150 pp m should be corrected to avoid that harmonics of the clk output disturb the receive mode. if the clk is not used, or carefully layouted on the application pcb (as needed for multi channel systems), more than 150 ppm can be compensated. the additional xto pulling is only 2 ppm, overtemperature and supply voltage. the xtal ver- sus temperature and it s aging is then the main source of frequency erro r in the local oscillator. the xto frequency depends on xtal properties and the load capacitances c l1, 2 at pin xtal1 and xtal2. the pulling of f xto from the nominal f xtal is calculated using the following formula: ppm. c m is the crystal's motional, c 0 the shunt and c ln the nominal load capacitance of the xtal found in its datasheet. c l is the total actual load capacitance of the crystal in the circuit and con- sists of c l1 and c l2 in series connection. table 8-2. typical measured supply current and output power in full-duplex mode 433.92 mhz/power amplifier is load optimized for +5 dbm, r 1 = 22k, pwrset = 20, (ba ttery application) v s = v s1 = v s2 = v sint 2.15v 3.0v 3.6v t amb = ?40c 10.2 ma/?6.2 dbm 10.9 ma/?5.2 dbm 11.4 ma/?4.6 dbm t amb = +25c 11.8 ma/?6.4 dbm 12.5 ma/?5.2 dbm 13.1 ma/?4.5 dbm t amb = +105c 13.4 ma/?7.5 dbm 14.2 ma/?5.9 dbm 14.8 ma/?5.0 dbm table 8-3. typical measured supply current and output power in full-duplex mode/ 433.92 mhz/power amplifier is load optimized for +5 dbm, r 1 = 22k, pwrset = 31, (car application) v s = v s2 = v sint 4.4v 5v 5.25v t amb = ?40c 13.6 ma/3.7 dbm 13.6 ma/3.7 dbm 13.6 ma/3.7 dbm t amb = +25c 15.6 ma/4.3 dbm 15.6 ma/4.3 dbm 15.6 ma/4.3 dbm t amb = +105c 17.6 ma/ 4.6 dbm 17.6 ma/4.6 dbm 17.6 ma/4.6 dbm p c m 2 ------- - c ln c l ? c 0 c ln + () c 0 c l + () ------------------------------------------------------------- 10 6 = 28 4829c?rke?09/05 ATA5823/ata5824 figure 9-1. xtal with load capacitances with c m 14 ff, c 0 1.5 pf, c ln = 9 pf and c l = 7.4 pf to 10.6 pf the pulling amounts to p 100 ppm and with c m 7 ff, c 0 1.5 pf, c ln = 9 pf and c l = 7.4 pf to 10.6 pf the pulling is p 50 ppm. since typical crystals have less than 50 ppm to lerance at 25c, the compensation is not critical and can, in both cases, be done with the 150 ppm. c 0 of the xtal has to be lower than c lmin /2 = 3.7 pf for a pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is a risk of an unstable oscillation. to ensure proper start-up behavior the small signal gain, and thus the negative resistance pro- vided by this xto at start is very large. for example oscillation starts up, even in worst case, with a crystal series resistance of 1.5 k ? at c 0 2.2 pf with this xto. the negative resistance is approximately given by with z 1 , z 2 as complex impedances at pin xtal1 and xtal2 hence z 1 = ? j/(2 f xto c l1 ) + 5 ? and z 2 = ? j/(2 f xto c l2 ) + 5 ? . z 3 consists of crystals c 0 in parallel with an internal 110 k ? resistor hence z 3 = ? j/(2 f xto c 0 ) /110 k ? , gm is the internal transconductance between xtal1 and xtal2 with typically 19 ms at 25c. with f xto = 13.5 mhz, gm = 19 ms, c l = 9 pf, c 0 = 2.2 pf this results in a negative resistance of about 2 k ? . the worst case for technological, supply voltage and temperature variations is then for c 0 2.2 pf always higher than 1.5 k ?. due to the large gain at start, the xto is able to meet a very low start- up time. the oscillation start-up time can be estimated with the time constant . after 10 to 20 , an amplitude detector detects the oscillation amplitude and sets xto_ok to high if the amplitude is large enough. this activates the clk output if clk_on and clk_en in control register 3 are high (see table 12-12 on page 39 ). note that the necessary conditions of the dvcc voltage also have to be fulfilled (see figure 9-2 on page 29 and figure 10-1 on page 31 ). xtal c l1 c l2 c 0 c m l m r m c l = c l1 c l2 /(c l1 + c l2 ) crystal equivalent circuit re z xtocore {} re z 1 z 3 z 2 z 3 z 1 + z 2 z 3 g m + z 1 z 2 z 3 z 1 z 2 g m +++ ----------------------------------------------------------------------------------------------------- - ?? ?? ?? = 2 4 2 f m 2 c m re z xtocore () r m + () ----------------------------------------------------------------------------------------------------------- = 29 4829c?rke?09/05 ATA5823/ata5824 to save current in idle and sleep mode, the load capacitors partially are switched off in this modes with s 1 and s 2 seen in figure 9-2 on page 29 . it is recommended to use a crystal with c m = 3.0 ff to 7.0 ff, c ln = 9 pf, r m < 120 ? and c 0 = 1.0 pf to 2.2 pf. lower values of c m can be used, this increases slightly the start-up time. lower values of c 0 or higher values of c m (up to 15 ff) can also be used, th is has only little influence to pulling. figure 9-2. xto block diagram to find the right values used in the control registers 2 and 3 (see table 12-7 on page 38 and table 12-10 on page 39 ) the relationship between f xto and the f rf is shown in table 9-1 . to determine the right content, the frequency at pin clk, as well as the output frequency at rf_out in ask mode can be measured, than the freq value can be calculated according to table 9-1 so that f rf is exactly the desired radio frequency. s 1 s 2 xtal1 xtal2 c l1 c l2 10 pf 10 pf divider /3 clk clk_en (control register 3) divider /16 f dclk f xto divider /1 /2 /4 /8 /16 f xdclk baud1 baud0 xlim 8 pf 8 pf in idle mode and during sleep mode (rx_polling) the switches s 1 and s 2 are open. amplitude detector xto_ok (to reset logic) clk_on (control register 3) & dvcc_ok (from power supply) 30 4829c?rke?09/05 ATA5823/ata5824 the variable freq depends on the bit pll_mode in control register 1 and the parameter freq2 and freq3, which are defined by the bits fr0 to fr12 in control register 2 and 3 and is calculated as follows: freq = freq2 + freq3 care must be taken with the harmonics of the clk output signal f clk , as well as to the harmonics produced by an microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the rf input. in a single channel system the use of freq = 3803 to 4053 ensures that harmonics of this signal do not disturb the receive mode. in a multichannel system the clk signal can either be not used or carefully layouted on the application pcb. the supply voltage of the microcontroll er must also be carefully bl ocked in a multichannel system. 9.1 pin clk pin clk is an output to clock a connecte d microcontroller. the clock frequency f clk is calculated as follows: the signal at clk output has a nominal 50% duty cycle. if the bit clk_en in control register 3 is set to 0, the clock is disabled permanently. if the bit clk_en is set to 1 and bit clk_on (contr ol register 3) is set to 0, the clock is disabled as well. if bit clk_on is set to 1 and thus the clock is enabled if the bit-check is ok (rx, rx poll- ing, fd mode (slave)), an event on pin n_pwr_on occurs or the bit power_on in the status register is 1. figure 9-3. clock timing table 9-1. calculation of f rf frequency (mhz) pin 6 433_n868 creg1 bit(4) fs f xto (mhz) f rf = f tx_ask = f rx f tx_fsk_l = f tx_fsk_l(fd) f tx_fsk_h f tx_fsk_h(fd) frequency resolution 315.0 avcc 1 12.73193 f rf - 18.65 khz f rf + 18.65 khz f rf + 208.23 khz 777.1 hz 868.3 gnd 0 13.41180 f rf - 19.64 khz f rf + 19.64 khz f rf + 206.26 khz 818.6 hz 433.92 avcc 0 13.25311 f rf - 19.41 khz f rf + 19.41 khz f rf + 203.74 khz 808.9 hz f xto 24 5 freq 24,5 + 16384 ---------------------------------- + , ?? ?? f xto 64 5 freq 24,5 + 16384 ---------------------------------- + , ?? ?? f xto 32 5 freq 24,5 + 16384 ---------------------------------- + , ?? ?? f clk f xto 3 ----------- = clk_on (control register 3) clk dvcc v dvcc = 1.6 v (typ) clk_en (control register 3) 31 4829c?rke?09/05 ATA5823/ata5824 9.2 basic clock cycle of the digital circuitry the complete timing of the digital circuitr y is derived from one clock. according to figure 9-2 on page 29 , this clock cycle t dclk is derived from the crystal oscilla tor (xto) in combination with a divider. t dclk controls the following application relevant parameters: timing of the polling circuit including bit-check tx baud rate the clock cycle of the bit-check and the tx baud rate depends on the selected baud-rate range (br_range) which is defined in control register 6 (see table 12-19 on page 41 ) and x lim which is defined in control register 4 (see table 12-16 on page 40 ). this clock cycle t xdclk is defined by the following formulas for further reference: br_range ? br_range 0: t xdclk = 8 t dclk x lim br_range 1: t xdclk = 4 t dclk x lim br_range 2: t xdclk = 2 t dclk x lim br_range 3: t xdclk = 1 t dclk x lim 10. power supply figure 10-1. power supply f dclk f xto 16 ----------- = v_reg 3.25 v typ. in out s r 1 1 n_pwr_on pwr_on offcmd q vs2 vs1 en avcc dvcc (command via spi) dvcc_ok (to xto and reset logic) sw_avcc sw_dvcc s r q 0 0 no change 0 1 0 1 0 1 1 1 1 ff1 vsint v_monitor (1.6 v typ.) & dvcc_ok xto_ok 32 4829c?rke?09/05 ATA5823/ata5824 the supply voltage range of the ATA5823/ata5824 is 2.15v to 3.6v or 4.4v to 5.25v. pin vs1 is the supply voltage input for the rang e 2.15v to 3.6v and is used in battery applica- tions using a single lithium 3v cell. pin vs2 is the voltage input for the range 4.4v to 5.25v (car applications), in this case the voltage regulator v_reg regulates vs1 to typically 3.25v. if the voltage regulator is active, a blocking capacit or of 2.2 f has to be connected to vs1. pin vsint is the voltage input for the microcontroller_interface and must be connected to the power supply of the microcontroller. the voltage range of v vsint is 2.25v to 5.25v (see figure 10-5 and figure 10-6 on page 35 ). avcc is the internal operation voltage of the rf transceiver and is feed via the switch sw_avcc by vs1. avcc must be blocked on pin avcc with a 68 nf capacitor (see figure 3-1 on page 6 , figure 4-1 on page 7 , figure 5-1 on page 8 and figure 6-1 on page 9 ). dvcc is the internal operation voltage of the digital control logic and is fed via the switch sw_dvcc by vs1. dvcc must be blocked on pin dvcc with 68 nf (see figure 3-1 on page 6 , figure 4-1 on page 7 , figure 5-1 on page 8 and figure 6-1 on page 9 ). pin pwr_on is an input to switch on the transceiver (active high). pin n_pwr_on is an input for a push button and can also be used to switch on the transceiver (active low). for current consumption reasons it is reco mmended to set n_pwr_on to gnd only tempo- rarily. otherwise an additional current flows because of a 50 k ? pull-up resistor. a voltage monitor generates the signal dvcc_ok if dvcc 1.6v typically. figure 10-2. flow chart operation modes avcc = off dvcc = off pin pwr_on = 1 or pin n_pwr_on = 0 off command and pin pwr_on = 0 and pin n_pwr_on = 1 avcc = vs1 dvcc = vs1 off mode idle mode opm2 opm1 opm0 0 0 1 tx mode 0 1 0 rx polling mode 0 1 1 rx mode 1 0 1 fd mode (master) 1 1 1 fd mode (slave) opm2 = 0 and opm1 = 0 and opm0 = 0 tx mode rx polling mode rx mode fd mode (slave) fd mode (master) avcc = vs1; dvcc = vs1 33 4829c?rke?09/05 ATA5823/ata5824 10.1 off mode after connecting the power supply (battery) to pin vs1 and/or vs2 and vsint, the transceiver is in off mode. in off mode avcc and dvcc are disabled, resulting in very low power con- sumption (i s_off is typically 10 na in the key fob application figure 3-1 on page 6 and figure 5-1 on page 8 and 0.5 a in the car application figure 4-1 on page 7 and figure 6-1 on page 9 ). in off mode the transceiver is not programmable via the 4-wire serial interface. 10.2 idle mode in idle mode avcc and dvcc are connected to the battery voltage (vs1). from off mode the transceiver changes to idle mode if pin pwr_on is set to 1 or pin n_pwr_on is set to 0. this state transition is indicated by an interrupt at pin irq and the status bits power_on = 1 or n_power_on = 1. in idle mode the rf transceiver is disabled and the power consumption i idle_vs1,2 is about 270 a (clk output off vs1 = vs2 = 3v). the exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the section ?electrical charac- teristics? for the appropriate application case. via the 4-wire serial interface a connect ed microcontroller can program the required parameter and enable the tx, rx polling, rx or fd mode.the transceiver can be set back to off mode by an off command via the 4-wire serial interface (the input level of pin pwr_on must be 0 and pin n_pwr_on = 1 before writing the off command) 10.3 reset timing and reset logic if the transceiver is switched on (off mode to idle mode) dvcc and avcc are ramping up as illustrated in figure 10-3 . the internal signal dvcc_reset resets the digital control logic and sets the control register to default values. bit dvcc_rst in the status register is set to 1. after v dvcc exceeds 1.6v (typically) and the start-up time of the xto is elapsed, the output clock at pin clk is available. dvcc_rst in the status register is set to 0 if v dvcc exceeds 1.6v, the start-up time of the xto is elapsed and the status register is read via the 4-wire serial interface. if v dvcc drops below 1.6v (typically) and pin n_pwr_on = 1 and pin pwr_on = 0 the trans- ceiver switches to off mode. table 10-1. control register 1 opm2 opm1 opm0 function 0 0 0 idle mode 34 4829c?rke?09/05 ATA5823/ata5824 figure 10-3. reset timing figure 10-4. reset logic 10.4 battery application the supply voltage range is 2.15v to 3.6v. figure 10-5. battery application dvcc, avcc dvcc_reset dvcc_rst (status register) 1.6 v (typ) clk v dvcc > 1.6 v and the xto is running read status register off mode idle, tx, rx, rx polling, fd mode off mode idle mode & dvcc_ok xto_ok dvcc_reset vs1 vs2 vsint microcontroller ATA5823/ata5824 vs 2.15 v to 3.6 v avcc dvcc cs sck sdi_tmdi sdo_tmdo irq clk out out out in in in microcontroller_interface rf transceiver digital control logic 35 4829c?rke?09/05 ATA5823/ata5824 10.5 car application the supply voltage range is 4.4v to 5.25v. figure 10-6. car application 11. microcontroller interface the microcontroller interface is a level converter wh ich converts all internal digital signals which are referred to the dvcc voltage, into the voltage used by the microcontroller. therefore, the pin vsint can be connected to the supply voltage of the microcontroller in the case the microcon- troller has another supply voltage than the ATA5823/ata5824. 12. digital control logic 12.1 register structure the configuration of the transceiver is stored in ram cells. the ram contains a 16 8-bit tx/rx data buffer and a 8 8-bit control register and is write and readable via a 4-wire serial interface (cs, sck, sdi_tmdi, sdo_tmdo). the 1 8-bit status register is not part of the ram a nd is readable via the 4-wire serial interface. the ram and the status information is stored as long as the transceiver is in any active mode (dvcc = vs1) and gets lost if the transceiver is in the off mode (dvcc = off). after the transceiver is turned on via pin pwr_on = high or pin n_pwr_on = low the control registers are in the default state. vs1 vs2 vsint microcontroller ATA5823/ata5824 vs 4.4 v to 5.25 v avcc dvcc cs sck sdi_tmdi sdo_tmdo irq clk out out out in in in microcontroller_interface rf transceiver digital control logic 36 4829c?rke?09/05 ATA5823/ata5824 figure 12-1. register structure msb lsb status register (adr 16) control register 1 (adr 0) control register 4 (adr 3) n_ power _on ---- bitch k1 bitch k0 ask_ nfsk sleep4 sleep3 sleep2 sleep1 sleep0 xsleep lim_ min5 lim_ min4 lim_ min3 lim_ min2 lim_ min1 lim_ min0 lim_ max5 lim_ max4 lim_ max3 lim_ max2 lim_ max1 lim_ max0 ir1 ir0 tx/rx data buffer: 16 8 bit opm1 opm2 t_ mode control register 5 (adr 4) control register 6 (adr 5) power _on opm0 control register 2 (adr 1) fr4fr3fr2fr1fr0 control register 3 (adr 2) fr9 fr8 dvcc _rst - fs pll_ mode fr5 fr6 p_ mode fr7 clk_ en clk_ on xlim baud 1 baud 0 tx5 tx4 tx3 tx2 tx1 tx0 control register 7 (adr 6) pout_ select pout_ data - = don't care pws et4 pws et3 pws et2 pws et1 pws et0 control register 8 (adr 7) - fe_ mode pws elect fr10 fr11 fr12 37 4829c?rke?09/05 ATA5823/ata5824 12.2 tx/rx data buffer the tx/rx data buffer is used to handle the data transfer during rx and tx operations. 12.3 control register to use the transceiver in different applications the transceiver can be configured by a microcon- troller connected via the 4-wire serial interface. 12.3.1 control register 1 (adr 0) table 12-1. control register 1 (function of bit 7 and bit 6 in rx mode) ir1 ir0 function (rx mode) 00 pin irq is set to 1 if 1 received byte is in the tx/rx data buffer or a receiving error occurred 01 pin irq is set to 1 if 2 received bytes are in the tx/rx data buffer or a receiving error occurred 10 pin irq is set to 1 if 4 received bytes are in the tx/rx data buffer or a receiving error occurred (default) 11 pin irq is set to 1 if 12 received bytes are in the tx/rx data buffer or a receiving error occurred table 12-2. control register 1 (function of bit 7 and bit 6 in tx mode) ir1 ir0 function (tx mode) 0 0 pin irq is set to 1 if 1 byte still is in the tx/rx data buffer or the tx data buffer is empty 01 pin irq is set to 1 if 2 bytes still are in t he tx/rx data buffer or the tx data buffer is empty 10 pin irq is set to 1 if 4 bytes still are in t he tx/rx data buffer or the tx data buffer is empty (default) 11 pin irq is set to 1 if 12 bytes still are in the tx/rx data buffer or the tx data buffer is empty note: the bits ir0 and ir1 have no function in fd mode table 12-3. control register 1 (function of bit 5) pll_mode function 0 adjustable range of freq: 3072 to 4095 (default), see table 12-10 on page 39 1 adjustable range of freq: 0 to 8191, see table 12-11 on page 39 table 12-4. control register 1 (function of bit 4) fs function (rx mode, tx mode, fd mode) 0 selected frequency 433/868 mhz (default) 1 selected frequency 315 mhz 38 4829c?rke?09/05 ATA5823/ata5824 12.3.2 control register 2 (adr 1) table 12-5. control register 1 (function of bit 3, bit 2 and bit 1) opm2 opm1 opm0 function 0 0 0 idle mode (default) 001tx mode 0 1 0 rx polling mode 0 1 1 rx mode 100- 1 0 1 full-duplex mode (master) 110- 1 1 1 full-duplex mode (slave) table 12-6. control register 1 (function of bit 0) t_mode function 0 tx and rx function via tx/rx data buffer (default) 1 transparent mode, tx/rx data buffer disa bled, tx modulation data stream via pin sdi_tmdi, rx modulation da ta stream via pin sdo_tmdo table 12-7. control register 2 (function of bit 7, bit 6, bit 5, bit 4, bit 3, bit 2 and bit 1) fr6 2 6 fr5 2 5 fr4 2 4 fr3 2 3 fr2 2 2 fr1 2 1 fr0 2 0 function 0000000freq2 = 0 0000001freq2 = 1 ....... 1 0 1 0 1 0 0 freq2 = 84 (default) ....... 1111111freq2 = 127 note: tuning of f rf lsb?s (total 13 bits), frequency trimming, resolution of f rf is f xto /16384 which is approximately 800 hz (see section ?xto?, table 9-1 on page 30 ) table 12-8. control register 2 (function of bit 0 in rx mode) p_mode function (rx mode) 0 pin irq is set to 1 if the bit-check is successful (default) 1 no effect on pin irq if the bit-check is successful table 12-9. control register 2 (function of bit 0 in tx mode) p_mode function (tx mode) 0 manchester modulator on (default) 1 manchester modulator off (nrz mode) note: bit p_mode has no function in fd mode 39 4829c?rke?09/05 ATA5823/ata5824 12.3.3 control register 3 (adr 2) table 12-10. control register 3 (function of bit 7, bit 6, bit 5, bit 4, bit 3 and bit 2 if bit pll_mode = 0 (in control register 1) fr12 2 12 fr11 2 11 fr10 2 10 fr9 2 9 fr8 2 8 fr7 2 7 function x x x 0 0 0 freq3 = 3072 x x x 0 0 1 freq3 = 3200 x x x 0 1 0 freq3 = 3328 x x x 0 1 1 freq3 = 3456 x x x 1 0 0 freq3 = 3584 x x x 1 0 1 freq3 = 3712 x x x 1 1 0 freq3 = 3840(default) x x x 1 1 1 freq3 = 3968 note: tuning of f rf msb?s table 12-11. control register 3 (function of bit 7, bit 6, bit 5, bit 4, bit 3 and bit 2 if bit pll_mode = 1 (in control register 1) fr12 2 12 fr11 2 11 fr10 2 10 fr9 2 9 fr8 2 8 fr7 2 7 function 000000freq3 = 0 000001freq3 = 128 000010freq3 = 256 ....... 0 1 1 1 1 0 freq3 = 3840 (default) ....... 111110freq3 = 7936 111111freq3 = 8064 note: tuning of f rf msb?s table 12-12. control register 3 (function of bit 1 and bit 0) clk_en clk_on function (rx mode, tx mode, fd mode) 0 x clock output off (pin clk) 10 clock output off (pin clk). clock switched on by an event: - bit-check ok or - event on pin n_pwr_on or - bit power_on in the status register is 1 1 1 clock output on (default) note: bit clk_on is set to 1 if the bit-check is ok (rx_polling, rx mode), an event at pin n_pwr_on occurs or the bit power_on in the status register is 1. 40 4829c?rke?09/05 ATA5823/ata5824 12.3.4 control register 4 (adr 3) 12.3.5 control register 5 (adr 4) table 12-13. control register 4 (function of bit 7) ask_nfsk function (tx mode, rx mode) 0 fsk mode (default) 1 ask mode note: bit ask_nfsk has no function in fd mode table 12-14. control register 4 (function of bit 6, bit 5, bit 4, bit 3 and bit 2) sleep4 2 4 sleep3 2 3 sleep2 2 2 sleep1 2 1 sleep0 2 0 function (rx mode) sleep (t sleep = sleep 1024 t dclk x sleep ) 00000 0 00001 1 ..... 11000 24 (t sleep = 24 1024 t dclk x sleep ) (default) ..... 11111 31 note: bits sleep0 ... sleep4 have no function in tx mode and fd mode table 12-15. control register 4 (function of bit 1) xsleep function 0x sleep = 1; extended t sleep off (default) 1x sleep = 8; extended t sleep on note: bit x sleep has no function in tx mode and fd mode table 12-16. control register 4 (function of bit 0) xlim function 0x lim = 1; extended t lim_min , t lim_max off (default) 1x lim = 2; extended t lim_min , t lim_max on note: bit x lim has no function in tx mode and fd mode table 12-17. control register 5 (function of bit 7 and bit 6) bitchk1 bitchk0 function 00n bit-check = 0 (0 bits checked during bit-check) 01n bit-check = 3 (3 bits checked during bit-check) (default) 10n bit-check = 6 (6 bits checked during bit-check) 11n bit-check = 9 (9 bits checked during bit-check) note: bits bitchk0 and bitchk1 have no function in tx mode and fd mode master 41 4829c?rke?09/05 ATA5823/ata5824 bits lim_min0 to lim_min5 have no function in tx mode and fd mode master. 12.3.6 control register 6 (adr 5) table 12-18. control register 5 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) lim_min5 2 5 lim_min4 2 4 lim_min3 2 3 lim_min2 2 2 lim_min1 2 1 lim_min0 2 0 function (rx mode, fd mode slave) lim_min (lim_min < 10 are not applicable) (t lim_min = lim_min t xdclk ) 001010 10 001011 11 (t lim_min = 11 t xdclk ) (default) ...... 111111 63 table 12-19. control register 6 (function of bit 7 and bit 6) baud1 baud0 function (rx mode, tx mode, fd mode) 00 baud-rate range 0 (b0) 1.0 kbaud to 2.5 kbaud; t xdclk = 8 t dclk x lim 01 baud-rate range 1 (b1) 2.0 kbaud to 5.0 kbaud; t xdclk = 4 t dclk x lim baud-rate in fd mode = 1 / (168 t dclk ) 10 baud-rate range 2 (b2) 4.0 kbaud to 10.0 kbaud; t xdclk = 2 t dclk x lim (default) 11 baud-rate range 3 (b3) 8.0 kbaud to 20.0 kbaud; t xdclk = 1 t dclk x lim note that the receiver is not working with >10 kbaud in ask mode table 12-20. control register 6 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) lim_max5 2 5 lim_max4 2 4 lim_max3 2 3 lim_max2 2 2 lim_max1 2 1 lim_max0 2 0 function (rx mode, fd mode slave) lim_max (lim_max < 12 are not applicable) (t lim_max = (lim_max - 1) t xdclk ) 001100 12 001101 13 ...... 100000 32 (t lim_max = (32 ? 1) t xdclk ) (default) ...... 111111 63 note: bits lim_max0 to lim_max5 have no function in tx mode and fd mode master 42 4829c?rke?09/05 ATA5823/ata5824 12.3.7 control register 7 (adr 6) 12.3.8 control register 8 (adr 7) table 12-21. control register 7 (function of bit 7 and bit 6) pout_select pout_data function (rx mode, tx mode, fd mode) 0 0 output level on pin pout = 0 (default) 0 1 output level on pin pout = 1 1 x output level on pin pout = n_rx_active (1) note: 1. idle, tx, fd mode: n_rx_active = 1 rx mode: n_rx_active = 0 table 12-22. control register 7(function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) tx5 2 5 tx4 2 4 tx3 2 3 tx2 2 2 tx1 2 1 tx0 2 0 function (tx mode) tx (tx < 10 are not applicable) (tx_baudrate = 1/(tx + 1) t xdclk 2) 001010 10 001011 11 ...... 010100 20 (tx_baudrate = 1/(20 + 1) t xdclk 2) (default) ...... 111111 63 note: bits tx0 to tx5 have no function in rx mode and fd mode table 12-23. control register 8 (function of bit 6) fe_mode function 0 for future use 1 bit for internal use, must always set to 1 (default) table 12-24. control register 8 (function of bit 5) pwselect function (tx mode, fd mode) 0 r pwset = 140 ? typically in tx-mode and as defined by the bits pwset0 to pwset4 in fd mode (default) 1r pwset as defined by the bits pwset0 to pwset4 43 4829c?rke?09/05 ATA5823/ata5824 normally the setpwr resistor at pin 19 is used in full-duplex mode to decrease the output power until the level at rf_in is low enough for reception of signals (pwselect = 0). with pwselect = 1 this resistor can also be used in normal half-duplex tx operation to adjust the output power for production tolerances. 12.3.9 status register (adr 16) the status register indicates the current status of the transceiver and is readable via the 4-wire serial interface. setting power_on or an event on n_power_on is indicated by an irq. reading the status register resets the bits power_on, dvcc_rst and the irq. table 12-25. control register 8 (function of bit 4, bit 3, bit 2, bit 1, bit 0) pwset4 2 4 pwset3 2 3 pwset2 2 2 pwset1 2 1 pwset0 2 0 function (tx mode, fd mode) (setpwr: programmable internal resistor to reduce the output power in fd and tx mode) pwset setpwr = 800 ? + (31 ? pwset) 3 k ? (typically) 00000 0 00001 1 ..... 10000 16 (default) setpwr = 800 ? + (31 ? 16) 3 k ? (typically) ..... 11110 30 11111 31 table 12-26. status register status bit function n_power_on status of pin n_pwr_on pin n_pwr_on = 0 n_power_on = 1 pin n_pwr_on = 1 n_power_on = 0 ( figure 12-3 on page 45 ) power_on indicates that the transceiver was woken up by pin pwr_on (rising edge on pin pwr_on). during power_on = 1, the bit clk_on in control register 3 is set to 1 ( figure 12-4 on page 46 ). dvcc_rst dvcc_rst is set to 1 if the supply voltage of the ram (v dvcc ) was too low and the information in the ram may be lost. dvcc_rst = 0 supply voltage of the ram ok dvcc_rst = 1 supply voltage of the ram was too low (typically v dvcc < 1.6v) if the transceiver changes from off mode to idle mode, dvcc_rst will be set to 1. reading the status register resets dvcc_rst to 0. 44 4829c?rke?09/05 ATA5823/ata5824 12.4 pin n_pwr_on to switch the transceiver from off to idle mode, pin n_pwr_on must be set to 0 (maximum 0.2 v vs2 ) for at least t n_pwr_on_irq (see figure 12-2 ). the transceiver recognizes the nega- tive edge and switches on dvcc and avcc. if v dvcc exceeds 1.6v (typically) and the xto is settled, the digital control logic is active and sets the status bit n_power_on to 1, an interrupt is issued (t n_pwr_on_irq ) and the output clock on pin clk is available. if the level on pin n_pwr_on was set to 1 before the interrupt is issued, the transceiver stays in off mode. note: it is not possible to set the transceiver to off-mode by setting pin n_pwr_on to 1. if pin n_pwr_on is not used, it should be left open because of the internal pull-up resistor figure 12-2. timing pin n_pwr_on, st atus bit n_power_on if the transceiver is in any of the active modes (idle, tx, rx, rx_polling, fd), an integrated debounce logic is active. if there is an event on pin n_pwr_on, a debounce counter is set to 0 (t = 0) and started. the status is updated, an interrupt is issued and the debounce counter is stopped after reaching the counter value t = 8195 t dclk . an event on n_pwr_on before reaching t = 8195 t dclk stops the debounce counter. while the debounce counter is running, the bit clk_on in control register 3 is set to 1. the interrupt is deleted after reading the status register or executes the command delete_irq. if pin n_pwr_on is not used, it can be left ope n because of an internal pull-up resistor (typi- cally 50 k ? ). n_pwr_on irq n_power_on (status register) clk off mode idle mode dvcc, avcc t n_pwr_on_irq 1.6 v (typ) 45 4829c?rke?09/05 ATA5823/ata5824 figure 12-3. timing flow pin n_pwr_on, status bit n_power_on 12.5 pin pwr_on to switch the transceiver from off to idle mode, pin pwr_on must set to 1 (minimum 0.8 v vsint ) for at least t pwr_on (see figure 12-4 on page 46 ). the transceiver recognizes the positive edge and switches on dvcc and avcc. if v dvcc exceeds 1.6v (typically) and the xto is settled, the digital control logic is active and sets the status bit power_on to 1, an interrupt is issued (t pwr_on_irq_1 ) and the output clock on pin clk is available. if the level on pin pwr_on was set to 0 before the interrupt is issued, the transceiver stays in off mode. if the transceiver is in any of the active modes (idle, rx, rx_po lling, tx, fd), a positive edge on pin pwr_on sets power_on to 1 (after t pwr_on_irq_2 ). the state transition power_on 0 1 generates an interrupt. if powe r_on is still 1 during the positiv e edge on pin pwr_on, no inter- rupt is issued. power_on and the interrupt is deleted after reading the status register. event on pin n_pwr_on ? n y event on pin n_pwr_on ? n y t = 8195 t dclk ? n y t = 0 start debounce counter stop debounce counter n_power_on = 1; irq = 1 pin n_pwr_on = 0 ? stop debounce counter n_power_on = 0; irq = 1 y n idle mode or tx mode or rx polling mode or rx mode or fd mode stop debounce counter 46 4829c?rke?09/05 ATA5823/ata5824 during power_on = 1, the bit clk_en in control register 3 is set to 1. note: it is not possible to set the transceiver to off mode by setting pin pwr_on to 0. if pin pwr_on is not used, it must be connected to gnd. figure 12-4. timing pin pwr_on, status bit power_on 12.6 dvcc_rst the status bit dvcc_rst is set to 1 if the voltage on pin dvcc v dvcc drops under 1.6v (typically). dvcc_rst is set to 0 if v dvcc exceeds 1.6v (typically) and the status register is read via the 4-wire serial interface (see figure 10-3 on page 34 ). pwr_on irq power_on (status register) clk off mode idle mode idle, rx, rx polling, tx, fd mode dvcc, avcc t pwr_on_irq_1 1.6 v (typ) t pwr_on_irq_2 t pwr_on > t pwr_on_irq_1 t pwr_on > t pwr_on_irq_2 47 4829c?rke?09/05 ATA5823/ata5824 figure 12-5. timing flow status bit dvcc_rst 13. transceiver configuration the configuration of the transceiver takes plac e via a 4-wire serial interface (cs, sck, sdi_tmdi, sdo_tmdo) and is organized in 8-bit units . the configuration is initiated with a 8-bit command. while shifting the command into pin sdi_tmdi, the number of bytes in the tx/rx data buffer are available on pin sdo_tmdo. the read and write commands are followed by one or more 8-bit data units. each 8-bit data transmission begins with the msb. 13.1 command: read tx/rx data buffer during a rx operation the user can read the received bytes in the tx/rx data buffer successively. figure 13-1. read tx/rx data buffer vdvcc < 1.6 v (typ) ? n y idle, tx, rx, rx polling, fd mode dvcc_rst = 1; read status register pin pwr_on = 1 or pin n_pwr_on = 0 ? y n off_mode command: read tx/rx data buffer sdi_tmdi sdo_tmdo no. bytes in the tx/rx data buffer sck x rx data byte 1 x rx data byte 2 cs msblsbmsblsb lsb msb 48 4829c?rke?09/05 ATA5823/ata5824 13.2 command: write tx/rx data buffer during a tx operation the user can write the bytes in the tx/rx data buffer successively. figure 13-2. write tx/rx data buffer 13.3 command: read cont rol/status register the control and status registers can be read individually or successively. figure 13-3. read control/status register 13.4 command: write control register the control registers can be written individually or successively. figure 13-4. write control register command: write tx/rx data buffer sck tx data byte 1 tx data byte 2 write tx/rx data buffer tx data byte 1 sdi_tmdi sdo_tmdo cs msb lsb msb lsb msb lsb no. bytes in the tx/rx data buffer command: read c/s register x sck data c/s register x sdi_tmdi sdo_tmdo cs msblsbmsblsb no. bytes in the tx/rx data buffer data c/s register y msb lsb command: read c/s register y command: read c/s register z command: write control register x sck data control register x write control register x sdi_tmdi sdo_tmdo cs msblsbmsblsb no. bytes in the tx/rx data buffer command: write control register y msb lsb data control register x 49 4829c?rke?09/05 ATA5823/ata5824 13.5 command: off command if the input level on pin pwr_on is low and on the key input n_pwr_on is high, the off com- mand sets the transceiver to the off mode. figure 13-5. off command 13.6 command: delete irq the delete irq command sets pin irq to low. figure 13-6. delete irq 13.7 command structure the three most significant bits of the command (bit 5 to bit 7) indicates the command type. bit 0 to bit 4 describes the target address when reading or writing to a control or status register. bit 0 to bit 4 in the command write tx/rx data buffer defines the value n (0 n 16). the tx operation only will be started if the number of bytes in the tx buffer n. this function makes sure that the datastream will be sent without g aps. the tx operation only will be started if at least 1 byte are in the tx buffer. this means that n = 0 and n = 1 have the same function. in all other commands bit 0 to bit 4 have no effect and should be set to 0 for compatibility rea- sons with future products. command: off command sck sdi_tmdi sdo_tmdo cs msb lsb no. bytes in the tx/rx data buffer command: delete irq sck sdi_tmdi sdo_tmdo cs msb lsb no. bytes in the tx/rx data buffer 50 4829c?rke?09/05 ATA5823/ata5824 13.8 4-wire serial interface the 4-wire serial interface consis ts of the chip select (cs), the serial clock (sck), the serial data input (sdi_tmdi) and the serial data output (sdo_tmdo). data is transmitted/received bit by bit in synchronization with the serial clock. pin cs_pol defines the active level of the cs: when cs is inactive and the transceiver is not in rx transparent mode, sdo_tmdo is in a high-impedance state. pins sck_pol and sck_pha defines the polarity and the phase of the serial clock sck. figure 13-7. serial timing sck_pol = 0, sck_pha = 0 table 13-1. command structure command msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read tx/rx data buffer 0 0 0 x x x x x write tx/rx data buffer 0 0 1 n4 n3 n2 n1 n0 read control/status register 0 1 0 a4 a3 a2 a1 a0 write control register 0 1 1 a4 a3 a2 a1 a0 off command 1 0 0xxxxx delete irq 1 0 1xxxxx not used 1 1 0xxxxx not used 1 1 1xxxxx table 13-2. active level of the cs cs_pol function 0 cs active high 1 cs active low cs sck sdi_tmdi sdo_tmdo t out_enable t setup xmsb t hold x msb t cycle t cs_setup msb-1 t out_delay msb-1 x t cs_disable t out_disable x lsb x x t sck_setup1 t sck_setup2 t sck_hold x can be either v il or v ih 51 4829c?rke?09/05 ATA5823/ata5824 figure 13-8. serial timing sck_pol = 0, sck_pha = 1 figure 13-9. serial timing sck_pol = 1, sck_pha = 0 figure 13-10. serial timing sck_pol = 1, sck_pha = 1 cs sck sdi_tmdi sdo_tmdo t out_enable t setup xmsb t hold x t cycle t cs_setup msb-1 t out_delay msb x t cs_disable t out_disable x lsb lsb msb-1 x t sck_setup1 x t sck_setup2 t sck_hold x can be either v il or v ih cs sck sdi_tmdi sdo_tmdo t out_enable t setup xmsb t hold x msb t cycle t cs_setup msb-1 t out_delay msb-1 x t cs_disable t out_disable x lsb x t sck_setup1 t sck_setup2 x t sck_hold x can be either v il or v ih cs sck sdi_tmdi sdo_tmdo t out_enable t setup xmsb t hold x t cycle t cs_setup msb-1 t out_delay msb x t cs_disable t out_disable x lsb lsb msb-1 x t sck_setup1 t sck_setup2 x t sck_hold x can be either v il or v ih 52 4829c?rke?09/05 ATA5823/ata5824 14. operation modes 14.1 rx operation the transceiver is set to rx operation with the bits opm0, opm1 and opm2 in control register 1 the transceiver is designed to consume less than 1 ma in rx operation while being sensitive to signals from a corresponding transmi tter. this is achieved via the polling circuit. this circuits enable the signal path periodically for a short time . during this time the bit-check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected the transceiver remains active and transfers the data to the connected microcontroller. this transfer take place either via the tx/rx data buffer or via the pin sdo_tmdo. if there is no valid signal present the transceiver is in sleep mode most of the time resulting in low current consumption. this condition is called rx polling mode. a c onnected microcontrolle r can be disabled during this time. all relevant parameters of the polling logic can be configured by the connected microcontroller. this flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate etc. in rx mode the rf transceiver is enabled perma nently and the bit-check logic verifies the pres- ence of a valid transmitter signal. if a valid signal is detected the transceiver transfers the data to the connected microcontroller. this transfer take s place either via the tx/rx data buffer or via the pin sdo_tmdo. 14.1.1 rx polling mode if the transceiver is in rx polling mode, it stays in a continuous cycle of th ree different modes. in sleep mode, the rf transceiver is disabled for the time period t sleep while consuming low cur- rent of i s = i idle_x . during the start-up period, t startup_pll and t startup_sig_proc , all signal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit versus a valid tr ansmitter signal. if no valid sig nal is present, the transceiver is set back to sleep mode after the period t bit-check . this period varies check by check as it is a sta- tistical process. an average value for t bit-check is given in the electrical characteristics. during t startup_pll the current consumption is i s = i rx_x . during t startup_sig_proc and t bit-check the current consumption is i s = i startup_sig_proc_x . the condition of the transceiver is indicated on pin rx_active (see figure 14-1 ). the average current consum ption in rx polling mode i poll is dif- ferent in battery application or car application. to calculate i poll the index x must be replaced by vs1,2 in battery application or vs2 in car application (see section ?electrical characteristics: general? on page 72 ). table 14-1. control register 1 opm2 opm1 opm0 function 0 1 0 rx polling mode 011 rx mode i poll i idle_x t sleep i startup_pll_x t startup_pll i rx_x t startup_sig_proc t bitcheck + () ++ t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - = 53 4829c?rke?09/05 ATA5823/ata5824 to save current it is recommended clk be disabled during rx polling mode. i p does not include the current of the microcontroller_interface i vsint . if clk is enab led during the rx polling mode the current consumption is calculated as follows: during t sleep , t startup_pll and t startup_sig_proc the transceiver is not sensitive to a transmitter sig- nals. to guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst t preburst depends on the polling parameters t sleep , t startup_pll , t startup_sig_proc and t bit-check . thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. 14.1.2 sleep mode the length of period t sleep is defined by the 5-bit word sleep in control register 4, the extension factor x sleep defined by the bit x sleep in control register 4 an d the basic clock cycle t dclk . it is cal- culated to be: in us and european applications, the maximum value of t sleep is about 38 ms if x sleep is set to 1 (which is done by setting the bit x sleep in control register 4 to 0). the time resolution is about 1.2 ms in that case. the sleep time can be extended to about 300 ms by setting x sleep to 8 (which is done by setting x sleep in control register 4 to 1), the time resolution is then about 9.6 ms. 14.1.3 start-up mode during t startup_pll the pll is enabled and starts up. if the pll is locked, the signal processing circuit starts up (t startup_sig_proc ). after the start-up time all ci rcuits are in stable condition and ready to receive. i s_poll i poll i vsint + = t preburst t sleep t startup_pll t startup_sig_proc t bitcheck ++ + t sleep sleep 1024 t dclk x sleep = 54 4829c?rke?09/05 ATA5823/ata5824 figure 14-1. flow chart rx polling mode/rx mode sleep mode: all circuits for analog signal processing are disabled. only xto and polling logic is enabled. output level on pin rx_active -> low; i s = i idle_x t sleep = sleep 1024 t dclk x sleep start-up signal processing: the signal processing circuit are enabled. output level on pin rx_active -> high; i s = i startup_sig_proc_x ; t startup_sig_proc bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the control bit clk_on and opm0 are set to 1 and the transceiver is set to receiving mode. otherwise it is set to sleep mode or to start-up mode. output level on pin rx_active -> high i s = i startup_sig_proc_x t bit-check receiving mode: the incomming data stream is passed via the tx/rx data buffer or via pin sdo_tmdo to the connected microcontroller. if an bit error occurs the transceiver is set back to start-up mode. output level on pin rx_active -> high i s = i s_rx start-up pll: the pll is enabled and locked. output level on pin rx_active -> high; i s = i startup_pll_x ;t startup_pll start-up mode: opm0=1 ? bit check ok ? yes no no yes set clk_on = 1 set opm0 = 1 start bit detected ? yes sleep: defined by bits sleep0 ... sleep4 in control register 4 x sleep : defined by bit xsleep in control register 4 t dclk : basic clock cycle t startup_pll : 798.5 t dclk (typ) t startup_sig_proc : 930 t dclk (br_range 0) 546 t dclk (br_range 1) 354 t dclk (br_range 2) 258 t dclk (br_range 3) is defined by the selected baud rate range and t dclk . the baud-rate range is defined by bit baud0 and baud1 in control register 6. t bit-check : depends on the result of the bit check. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t xdclk . the baud-rate range is defined by bit baud0 and baud1 in control register6. t_mode = 0 and p_mode = 0 ? yes set irq no start rx polling mode start rx mode t_mode = 1 and level on pin cs = inactive ? yes no rx data stream available on pin sdo_tmdo rx data stream is written into the tx/rx data buffer bit error ? yes t sleep =0 ? no yes no no if the transparent mode is not active and the transceiver detects a bit error after a successful bit check and before the start bit is detected pin irq will be set to high and the transceiver is set back to start-up mode. 55 4829c?rke?09/05 ATA5823/ata5824 14.1.4 bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subsequent time frame checks where the distance between 2 signal edges are continuously compared to a pro- grammable time window. the maximum count of th is edge to edge test before the transceiver switches to receiving mode is also programmable. 14.1.5 bit-check configuration assuming a modulation scheme that contains 2 edg es per bit, two time frame checks are verify- ing one bit. this is valid for manchester, bi-phase and most other modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in control register 5. this implies 0, 6, 12 and 18 edge to edge checks respectively. if n bit-check is set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. in the presence of a valid transmitter signal , the bit-check takes less time if n bit-check is set to a lower value. in rx polling mode, the bi t-check time is not dependent on n bit-check if no valid signal is present. figure 14-2 shows an example where 3 bi ts are tested successful. figure 14-2. timing diagram for complete successful bit-check according to figure 14-3 , the time window for the bit-check is defined by two separate time lim- its. if the edge to edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than limit t lim_min or exceeds t lim_max , the bit-check will be term inated and the transceive r switches to sleep mode. figure 14-3. valid time window for bit-check rx_active bit-check demod_out (number of checked bits: 3) t startup_sig_proc 1/2 bit bit-check ok t bit-check start-up mode bit-check mode 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit receiving mode demod_out t ee t lim_min 1/f signal t lim_max 56 4829c?rke?09/05 ATA5823/ata5824 for the best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a ?11111...? or a ?10101...? sequence in manchester or bi-phase is a good choice concerning that advice. a good compromise betw een sensitivity and susceptib ility to noise regarding the expected edge to edge time t ee is a time window of 38%. to get the maximum sensitivity the time window should be 50% and then n bit-check 6. using preburst patterns that contain various edge to edge time periods, the bit-check limits must be programmed according to the required span. the bit-check limits are determined by means of the formula below: t lim_min = lim_min t xdclk t lim_max = (lim_max -1) t xdclk lim_min is defined by the bits lim_min 0 to lim_min 5 in control register 5. lim_max is defined by the bits lim_max 0 to lim_max 5 in control register 6. using the above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xdclk . the time resolution defining t lim_min and t lim_max is t xdclk . the minimum edge to edge time t ee is defined according to the section ?receiving mode? on page 58 . the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. figure 14-4 , figure 14-5 and figure 14-6 on page 57 illustrate the bit-check for the bit-check limits lim_min = 14 and lim_max = 24. the signal processing circuits are enabled during t startup_pll and t startup_sig_proc . the output of the ask/fsk demodulator (d emod_out) is unde- fined during that period. when the bit-check be comes active, the bit-check counter is clocked with the cycle t xdclk . figure 14-4 shows how the bit-check proceeds if the bit-check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 14-5 on page 57 the bit-check fails as the value cv_lim is lower than the limit lim_min. the bit-check also fails if cv_lim reaches li m_max. this is illustrated in figure 14-6 on page 57 . figure 14-4. timing diagram during bit-check rx_active bit-check demod_out bit-check counter 1 234567812345678910111213141516171812345678910 11 0 12 13 14 15 1 2 3 4 (lim_min = 14, lim_max = 24) t startup_sig_proc 1/2 bit 1/2 bit 1/2 bit bit-check ok bit-check ok 5 67 t bit-check start-up mode bit-check mode t xdclk 57 4829c?rke?09/05 ATA5823/ata5824 figure 14-5. timing diagram for failed bit-check (condition cv_lim < lim_min) figure 14-6. timing diagram for failed bit-check (condition: cv_lim lim_max) 14.1.6 duration of the bit-check if no transmitter is pr esent during the bit-chec k, the output of the ask/fsk demodulator delivers random signals. the bit-check is a statistical process and t bit-check varies for each check. there- fore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected baud rate range and on t xdclk . a higher baud-rate range causes a lower value for t bit-check resulting in a lower current consumption in rx polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that sig- nal, f signal , and the count of the bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . rx_active bit-check demod_out bit-check counter 1 2345678123456789101112 0 0 (lim_min = 14, lim_max = 24) t startup_sig_proc 1/2 bit bit check failed (cv_lim < lim_min) t bit-check start-up mode bit-check mode t sleep sleep mode rx_active bit-check demod_out bit-check counter 1 2345678123456789101112 0 0 (lim_min = 14, lim_max = 24) t startup_sig_proc 1/2 bit bit-check failed (cv_lim lim_min) t bit-check start-up mode bit-check mode t sleep sleep mode 13 14 15 16 17 18 19 20 21 22 23 24 58 4829c?rke?09/05 ATA5823/ata5824 14.1.7 receiving mode if the bit-check was successful for all bits specified by n bit-check , the transceiver switches to receiving mode. to activate a connected microcontr oller, bit clk_on in co ntrol register 3 is set to 1. an interrupt is issued at pin irq if the control bits t_mode = 0 and p_mode = 0. if the transparent mode is active (t_mode = 1) and the level on pin cs is inactive (no data transfer via the serial interface), the rx data stream is available on pin sdo_tmdo ( figure 14-7 ). figure 14-7. receiving mode (tmode = 1) if the transparent mode is inactive (t_mode = 0), the received data stream is buffered in the tx/rx data buffer (see figure 14-8 on page 59 ). the tx/rx data buffer is only usable for manchester and bi-phase coded signals. it is perm anently possible to transfer the data from the data buffer via the 4-wire serial interface to a microcontroller (see figure 13-1 on page 47 ). buffering of the data stream: after a successful bit-check, the transceiver swit ches from bit-check mode to receiving mode. in receiving mode the tx/rx data buffer control logic is active and examines the incoming data stream. this is done, like in the bit-check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window as illustrated in figure 14-8 on page 59 . only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit-check. they can be programmed in control register 5 and 6 (lim_min, lim_max). the limits for 2t are calculated as follows: lower limit of 2t: upper limit of 2t: if the result of lim_min_2t or lim_max_2t is not an integer value, it will be round up. if the tx/rx data buffer control logic detects the start bit, the data stream is written in the tx/rx data buffer byte by byte. the start bit is part of the first data byte and must be different from the bits of the preburst. if the preburst consists of a sequence of ?00000...?, the start bit must be a 1. if the preburst consists of a sequence of ?11111...?, the start bit must be a 0. demod_out preburst start- bit 0000000001 1 0 0000011110 byte 1 byte 2 byte 3 0 11 0 10 1 10 0 bit-check ok sdo_tmdo bit-check mode receiving mode lim_min_2t lim_min lim_max + () lim_max lim_min ? () 2 ? ? = t lim_min_2t lim_min_2t t xdclk = lim_max_2t lim_min lim_max + () lim_max lim_min ? () 2 ? + = t lim_max_2t (lim_max_2t 1 ) ? t xdclk = 59 4829c?rke?09/05 ATA5823/ata5824 if the data stream consists of more than 16 bytes, a buffer overflow occurs and the tx/rx data buffer control logic overwrites the bytes already st ored in the tx/rx data buffer. so it is very important to ensure that the data is read in time so that no buffer overflow occurs in that case (see figure 13-1 on page 47 ). there is a counter that indicates the number of received bytes in the tx/rx data buffer (see section ?transceiver configuration? on page 47 ). if a byte is trans- ferred to the microcontroller, the counter is decre mented, if a byte is received, the counter is incremented. the counter value is ava ilable via the 4-wire serial interface. an interrupt is issued if the counter while counting forwards reaches the value defined by the control bits ir0 and ir1 in control register 1. figure 14-8. receiving mode (tmode = 0) if the tx/rx data buffer control logic detects a bit error, an interrupt is issued and the transceiver is set back to the start-up mode (see figure 14-1 on page 54 and figure 14-9 ). bit error: a) t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t b) logical error (no edge detected in the bit center) note: the byte consisting of the bit error will not be stored in the tx/rx data buffer. thus it is not avail- able via the 4-wire serial interface. writing the control register 1, 4, 5, 6 or 7 during receiving mode resets the tx/rx data buffer control logic and the counter which indicates the number of received bytes. if the bits opm0 and opm1 are still 1 and opm2 is still 0 after writing to a control register, th e transceiver changes to the start-up mode (start-up signal processing). figure 14-9. bit error (tmode = 0) demod_out preburst start- bit '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' byte 1 byte 2 byte 3 '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' tx/rx data buffer byte 1, byte17, ... byte 2, byte 18, ... byte 3, byte 19, ... byte 4, byte 20, ... byte 5, byte 21, ... byte 7, byte 23, ... byte 8, byte 24, ... byte 9, byte 25, ... byte 10, byte 26, ... byte 11, byte 27, ... byte 12, byte 28, ... byte 13, byte 29, ... byte 14, byte 30, ... byte 15, byte 31, ... byte 16, byte 32, ... byte 6, byte 22, ... bit-check ok 01000001 11100110 msb lsb readable via 4-wire serial interface bit-check mode receiving mode 2t t 111 000 demod_out byte n-1 byte n byte n+1 start-up mode receiving mode bit error bit-check mode receiving mode preburst bit-check ok byte 1 60 4829c?rke?09/05 ATA5823/ata5824 14.1.8 recommended lim_min and lim_max for maximum sensitivity the sensitivity measurement in the section ?low-if receiver? on page 10 , in table 7-3 and table 7-4 on page 12 have been done with the lim_min and lim_max values according to table 14-3 . these values are optimized for maximum sensit ivity. note that since these limits are opti- mized for sensitivity the number of checked bit n bit-check has to be at least 6 to prevent the circuit from waking up too often in polling mode due to noise. table 14-2. rx demodulation scheme mode ask/_nfsk t_mode rf in bit in tx/rx data buffer level on pin sdo_tmdo rx 0 0f fsk_l f fsk_h 1x 0f fsk_h f fsk_l 0x 1f fsk_h -1 1f fsk_l -0 1 0f ask off f ask on 1 x 0f ask on f ask off 0 x 1f ask on - 1 1f ask off - 0 table 14-3. recommended lim_min and lim_max values for different baud rates f rf (f xtal )/ mhz 1.0 kbaud br_range_0 xlim = 1 2.4 kbaud br_range_0 xlim = 0 5 kbaud br_range_1 xlim = 0 10 kbaud br_range_2 xlim = 0 20 kbaud br_range_3 xlim = 0 315 (12.73193) lim_min = 13 (251 s) lim_max = 38 (715 s) lim_min = 12 (121 s) lim_max = 34 (332 s) lim_min = 11 (55 s) lim_max = 32 (156 s) lim_min = 11 (28 s) lim_max = 32 (78 s) lim_min = 11 (14 s) lim_max = 32 (39 s) 433.92 (13.25311) lim_min = 13 (251 s) lim_max = 38 (715 s) lim_min = 11 (106 s) lim_max = 32 (299 s) lim_min = 11 (53 s) lim_max = 32 (150 s) lim_min = 11 (27 s) lim_max = 32 (75 s) lim_min = 11 (13 s) lim_max = 32 (37 s) 868.3 (13.41191) lim_min = 13 (248 s) lim_max = 38 (706 s) lim_min = 12 (115 s) lim_max = 34 (315 s) lim_min = 11 (52 s) lim_max = 32 (148 s) lim_min = 11 (26 s) lim_max = 32 (74 s) lim_min = 11 (13 s) lim_max = 32 (37 s) 61 4829c?rke?09/05 ATA5823/ata5824 14.2 tx operation the transceiver is set to tx operation by usi ng the bits opm0, opm1 and opm2 in the control register 1. before activating the tx mode, the tx parameters (baud rate, modulation scheme...) must be selected as illustrated in figure 14-10 on page 62 . the baud rate depends on baud 0 and baud 1 in control register 6 and tx0 to tx5 in control register 7 (see section ?control register? on page 37 ). the modulation is selected with ask_nfsk in control register 4. the fsk fre- quency deviation is fixed to about 19 khz (see table 9-1 on page 30 ). if p_mode is set to 1, the manchester modulator is disabled and pattern mode is active (nrz, see table 14-5 on page 64 ). after the transceiver is set to tx mode the start-up mode is active and the pll is enabled. if the pll is locked, the tx mode is active. if the transceiver is in start-up or tx mode, the tx/rx data buffer can be loaded via the 4-wire serial interface. after n bytes are in the buffer and the tx mode is active, the transceiver starts transmitting automatically (beginning with the msb). bit 0 to bit 4 in the command write tx/rx data buffer defines the value n (0 n 16; see section ?command structure? on page 49 ). while transmitting, it is permanently possible to load new data in the tx/rx data buffer. to pre- vent a buffer overflow or interruptions during transmitting the user must ensure that data is loaded at the same speed as it is transmitted. there is a counter that indicates the number of bytes to be transmitted (see section ?transceiver configuration? on page 47 ). if a byte is loaded, the counter is incremented, if a byte is transmit- ted, the counter is decremented. the counter value is available via the 4-wire serial interface. an irq is issued if the counter reaches the value de fined by the control bits ir0 and ir1 in control register 1. note: writing to the control register 1, 4, 5, 6 or 7 during tx mode, resets the tx/rx data buffer and the counter which indicates the number of bytes to be transmitted. if t_mode in control register 1 is set to 1, the transceiver is in tx transparent mode. in this mode the tx/rx data buffer is disabled and the tx data stream must be applied on pin sdi_tmdi. figure 14-10 on page 62 illustrates the flow chart of the tx transparent mode. table 14-4. control register 1 opm2 opm1 opm0 function 0 0 1 tx mode 62 4829c?rke?09/05 ATA5823/ata5824 figure 14-10. tx operation (t_mode = 0) n write control register 6 baud1, baud0: select baudrate range lim_max0 ... lim_max5: don't care write control register 5 bitchk1, bitchk0: don't care lim_min0 ... lim_min5: don't care write control register 4 ask/_nfsk: select modulation. sleep0 ... sleep4: don't care xsleep: don't care xlim: don't care write control register 3 fr7, fr8, fr9: adjust f rf clk_en, clk_on: application defined. write control register 2 fr0 ...fr6: adjust f rf p_mode: enable or disable the manchester modulator write control register 1 ir1, ir0: select an event which activates an interrupt pll_mode: set pll_mode = 0 fs: select operating frequency opm2, opm1, opm0: set opm2 = 0, opm1 = 0 and opm0 = 1 t_mode: set t_mode = 0 write tx/rx data buffer (max. 16 byte) pin irq=1 ? y n tx more data bytes ? y write tx/rx data buffer (max. 16 - number of bytes still in the tx/rx data buffer) command: delete_irq n pin irq=1 ? y write control register 1 opm2, opm1, opm0: set idle idle mode start-up mode (tx) t startup = 331.5 t dclk tx mode idle mode write control register 7 pout_select, pout_data: application defined. tx0 ... tx5: select the baud rate write control register 8 fe_mode: set fe_mode = 1 pwselect: set pwselect = 1 to reduce the output power with setpwr. pwset0 ... pwset4: adjust setpwr. don't care if pwselect = 0. 63 4829c?rke?09/05 ATA5823/ata5824 figure 14-11. tx transparent mode (t_mode = 1) write control register 4 ask/_nfsk: select modulation. sleep0 ... sleep4: don't care. xsleep: don't care. xlim: don't care. write control register 3 fr7, fr8, fr9: adjust f rf clk_en, clk_on: application defined. write control register 2 fr0 ...fr6: adjust f rf p_mode: don't care. write control register 1 ir1, ir0: don't care. pll_mode: set pll_mode = 0 fs: select operating frequency opm2, opm1, opm0: set opm2 = 0, opm1 = 0 and opm0 = 1. t_mode: set t_mode = 1 write control register 1 opm2, opm1, opm0: set idle idle mode start-up mode (tx) t startup = 331.5 t dclk tx mode idle mode apply tx data on pin sdi_tmdi write control register 7 pout_select, pout_data: application defined. tx0 ... tx5: don't care. write control register 6 baud1, baud0: don't care. lim_max0 ... lim_max5: don't care. write control register 5 bitchk1, bitchk0: don't care. lim_min0 ... lim_min5: don't care. write control register 8 fe_mode: set fe_mode = 1 pwselect: set pwselect = 1 to reduce the output power with setpwr. pwset0 ... pwset4: adjust setpwr. don't care if pwselect = 0. 64 4829c?rke?09/05 ATA5823/ata5824 14.3 full-duplex operation the transceiver is set to f ull- d uplex mode (fd mode) by using the bits opm0, opm1 and opm2 in the control register 1. in fd mode 2 transceiver exchange the content of the tx buffer simul- taneously. one transceiver must be configured as master and one as slave. before activating fd mode in both transceivers, the baud rate must be selected in control register 6 (baud1 = 0, baud0 = 1). additionally, in the slave the limits for the bit-check and the number of bits to be checked during the bit-check n bit-check must be adjusted in control register 5 and 6 (lim_min0 ... lim_min5, lim_max0 ... lim_max5, bitchk0, bitchk1). after activating the fd mode in control register 1, both transceivers are in the startup mode. dur- ing the startup mode, in master and slave, the tx data stream can be written in the tx buffer. in the master the tx data stream consists of preburst, startbit, synchronization pattern (3 bytes) and maximally 8 bytes of data. the preburst contains a sequence of ?11111...?. the minimum applicable preburst length is 15 bits and can be ex tended in 8 bit steps up to 95 bits. the value of the start bit is fixed and must be a 0. the position of the start bit is the lsb in the last byte of the preburst. the synchronization pattern contains 3 bytes with a fixed value (byte1: ff hex, byte2: 00 hex, byte3: 00 hex). the data block is user defined and contains maximally 8 bytes. if the preburst contains more than 39 bits the area for the data block will be equally reduced ( fig- ure 14-12 on page 65 .) in the slave the tx data stream consists of the synchronization pattern (3 bytes) and also maxi- mally 8 bytes of data. the synchronization pattern contains 3 bytes with a fixed value (byte1: 00 hex, byte2: 7f hex, byte3: ff hex). the dat a block is user defined and contains maximally 8 bytes ( figure 14-12 on page 65 ). the length of the data block must be equal in the master and slave. table 14-5. tx modulation schemes mode ask/_nfsk p_mode t_mode bit in tx/rx data buffer level on pin sdi_tmdi rf out tx 0 001xf fsk_l f fsk_h 000xf fsk_h f fsk_l 101x f fsk_h 100x f fsk_l x1x1 f fsk_h x1x0 f fsk_l 1 001xf ask off f ask on 000xf ask on f ask off 101x f ask on 100x f ask off x1x1 f ask on x1x0 f ask off table 14-6. control register 1 opm2 opm1 opm0 function 1 0 1 full-duplex mode (master) 1 1 1 full-duplex mode (slave) 65 4829c?rke?09/05 ATA5823/ata5824 if the time t startup-pll-fd (798.5 t dclk ) is elapsed the pll is enabled and locked. the master activates the power amplifier (pa) and starts transmitting the preburst, startbit, syn- chronization pattern and data block, when the pll is locked and at least n bytes are in the tx buffer. bit 0 to bit 4 in the command write tx/rx data buffer defines the value n (0 n 16; see section ?command structure? on page 49 ). if the pll is locked, the slave activates the pa and enables the analog si gnal processing. after t startup-sig-proc-fd (546 t dclk ) the analog signal processing is settled and the slave begins with the bit-check. if the bit-check was successful, the start bit was detected and at least n bytes are in the tx buffer, the slave starts transmitting the synchronization pattern and the data block. while transmitting the synchronization pattern, a synchronization procedure synchronizes both transceivers. thus master and slave are synchronized while transmitting the data block. if the tx buffer is empty, an interrupt will be issued and the pa will be sw itched off after the time t delay (168 t dclk ). t delay is implemented because of different internal delays in the rx signal path in master and slave. while transmitting the data block, the receiving data is ex-or-ed with the transmitting data and the result is written in the rx buffer. thus, afte r the fd operation the tx data of the slave is in the rx buffer of the master and the tx data of the master is in the rx buffer of the slave. after recognizing the interrupt, the microcontroller can read out the received data from the tx/rx data buffer. during writing the command ?read tx/rx data buffer? the number of received bytes in the buffer is issued on pin sdo_tmdo. after reading the tx/rx data buffer the transceiver should be set to the idle mode. figure 14-12. tx buffer fd mode preburst (ff hex) tx buffer master tx buffer slave 11111111 11111110 11111111 11111111 11111111 preburst (ff hex) preburst (ff hex) preburst (ff hex) preburst and start bit (fe hex) 11111111 00000000 00000000 synchronization byte 1 (ff hex) synchronization byte 2 (00 hex) synchronization byte 3 (00 hex) xxxxxxxx data byte 1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 00000000 xxxxxxxx 01111111 11111111 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx synchronization byte 1 (00 hex) synchronization byte 2 (7f hex) synchronization byte 3 (ff hex) data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 39 bits preburst 1 start bit 3 bytes synchronization pattern 8 bytes data 3 bytes synchronization pattern 8 bytes data msb lsb msb lsb 66 4829c?rke?09/05 ATA5823/ata5824 the timing of the fd mode is illustrated in figure 14-13 on page 67 . a proper data transfer takes place if the fd mode is enabled in the slave befor e it is enabled in the master. if the fd mode is enabled in the master before it is enabled in the slave, a maximum delay t fd_sync is allowed for a proper operation. t fd_sync depends on the preburst length and the number of bits to be checked during the bit-check. this is calculated as follows: t fd_sync < t preburst - t startup-sig-proc-fd - t bit-check-min this means, to get a extended time period for enabling the fd mode, increase the preburst length in the master and reduce n bit-check in the slave. the reference points for t fd_sync are the sampling edge (pin sck) for the l sb while writing control register 1. for a proper operation in the slave, a wake-up due to noise must be prevent (bit check + start bit ok). to achieve this for the slave th e following adjustments are recommended: 1. set n bit-check 6 2. start fd mode in master and slave as simultaneously as possible. table 14-7. t bit-check-min n bit-check t bit-check-min 34 168 t dclk 6 (recommended) 7 168 t dclk 910 168 t dclk 67 4829c?rke?09/05 ATA5823/ata5824 figure 14-13. timing full-duplex mode startup (t startup_pll_fd = 798.5 t dclk ) synchronization (t sync = 24 168 t dclk ) master bit-check (t bit-check ) slave t fd_sync t pin irq = 1; pa disabled delay read data from rx buffer master and slave synchron enable fd mode n bits preburst (t preburst = n 168 t dclk ) startbit (t startbit = 168 t dclk ) n bits data (t data = n 168 t dclk ) delay (t delay = 168 t dclk ) set transceiver to idle mode enable fd mode startup (t startup_pll_fd = 798.5 t dclk ) startup analog signal processing (t startup_sig_proc_fd = 546 t dclk ) pa enabled and at least n byte in tx buffer pa enabled synchronization start bit data pin irq = 1; pa disabled read data from rx buffer set transceiver to idle mode t bitcheck_min at least n byte in tx buffer 68 4829c?rke?09/05 ATA5823/ata5824 figure 14-14. flow fd mode (master) write control register 4 ask/_nfsk: dont' care sleep0 ... sleep4: don't care xsleep: don't care xlim: don't care write control register 3 fr7, fr8, fr9: adjust f rf clk_en, clk_on: application defined write control register 2 fr0 ...fr6: adjust f rf p_mode: don't care write control register 1 ir1, ir0: don't care pll_mode: application defined fs: select operating frequency opm2, opm1, opm0: set opm2 = 1, opm1 = 0, opm0 = 1 t_mode: t_mode = 0 write control register 1 opm2, opm1, opm0: set idle idle mode start-up fd mode (master) t startup_pll_fd = 798.5 t dclk fd mode (master) idle mode write control register 7 pout_select, pout_data: application defined. tx0 ... tx5: don't care write control register 6 baud1, baud0: set baud1 = 0, baud0 = 1 lim_max0 ... lim_max5: don't care write control register 5 bitchk1, bitchk0: don't care lim_min0 ... lim_min5: don't care write control register 8 fe_mode: set fe_mode = 1 pwselect: don't care pwset0 ... pwset4: adjust setpwr to reduce the output power write tx/rx buffer (preburst, startbit, synchronization pattern, data block) (max. 16 byte) n pin irq=1 ? y read tx/rx buffer 69 4829c?rke?09/05 ATA5823/ata5824 figure 14-15. flow fd mode (slave) write control register 4 ask/_nfsk: dont' care sleep0 ... sleep4: don't care xsleep: don't care xlim: don't care write control register 3 fr7, fr8, fr9: adjust f rf clk_en, clk_on: application defined write control register 2 fr0 ...fr6: adjust f rf p_mode: don't care write control register 1 ir1, ir0: don't care pll_mode: application defined fs: select operating frequency opm2, opm1, opm0: set opm2 = 1, opm1 = 1, opm0 = 1 t_mode: t_mode = 0 write control register 1 opm2, opm1, opm0: set idle idle mode start-up fd mode (slave) t startup_pll_fd = 798.5 t dclk fd mode (slave) idle mode write control register 7 pout_select, pout_data: application defined tx0 ... tx5: don't care write control register 6 baud1, baud0: baud1 = 0, baud0 = 1 lim_max0 ... lim_max5: lim_max5 = 1, lim_max4 = 0, lim_max3 = 0, lim_max2 = 0, lim_max1 = 0, lim_max0 = 0 write control register 5 bitchk1, bitchk0: bitchk1 = 1, bitchk0 = 0 lim_min0 ... lim_min5: lim_min5 = 0, lim_min4 = 0, lim_min3 = 1, lim_min2 = 0, lim_min1 = 1, lim_min0 = 1 write control register 8 fe_mode: set fe_mode = 1 pwselect: don't care pwset0 ... pwset4: adjust setpwr to reduce the output power write tx/rx buffer (synchronization pattern, data block) (max. 9 byte) n pin irq=1 ? y read tx/rx buffer t startup-sig-proc-fd = 546 t dclk 70 4829c?rke?09/05 ATA5823/ata5824 14.4 interrupts via pin irq, the transceiver signals different operating conditions to a connected microcontrol- ler. if a specific operating condition o ccurs, pin irq is set to a high level. if an interrupt occurs, it is recommended to dele te the interrupt immediately by reading the sta- tus register, thus the next possible interrupt doesn? t get lost. if the interrupt pin doesn?t switch to a low level by reading the status register, the interrupt was triggered by the rx/tx data buffer. in this case, read or write the rx/tx data buffer according to table 14-8 . table 14-8. interrupt handling operating conditions which sets pin irq to high level operations which sets pin irq to low level events in status register state transition of status bit n_power_on (0 1; 1 0) read status register or command delete irq appearance of status bit power_on (0 1) events during tx operation (t_mode = 0) 1, 2, 4 or 12 bytes are in the tx data buffer or the tx data buffer is empty (depends on ir0 and ir1 in control register 1) write tx data buffer or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq events during rx operation (t_mode = 0) 1, 2, 4 or 12 received bytes are in the rx data buffer or a receiving error is occurred (depends on ir0 and ir1 in control register 1) read rx data buffer or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq successful bit-check (p_mode = 0) events during fd operation tx data buffer empty read rx data buffer or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq 71 4829c?rke?09/05 ATA5823/ata5824 15. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any othe r conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c supply voltage vs2 v maxvs2 ?0.3 +7.2 v supply voltage vs1 v maxvs1 ?0.3 +4 v supply voltage vsint v maxvsint ?0.3 +5.5 v esd (human body model esd s.5.1) every pin hbm ?2.5 +2.5 kv esd (machine model jedec a115a) every pin mm ?200 +200 v esd (field induced charge device model esd stm 5.3.1-1999) every pin fcdm ?500 500 v maximum input level, input matched to 50 ? p in_max 10 dbm 16. thermal resistance parameters symbol value unit junction ambient r thja 25 k/w 72 4829c?rke?09/05 ATA5823/ata5824 17. electrical charac teristics: general all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* 1 rx_tx_idle mode 1.1 rf operating frequency range ata5824 v 433_n868 = gnd 4, 10 f rf 867 870 mhz a ata5824 v 433_n868 = avcc 4, 10 f rf 433 435 mhz a ata 5 8 2 3 v 433_n868 = avcc 4, 10 f rf 314 316 mhz a 1.2 supply current off mode v vs1 = v vs2 = v vsint = 3v (battery) 17, 18, 27 i s_off < 10 na a v vs2 = v vsint = 5v (car) 17, 27 i s_off < 10 na a 1.3 supply current idle mode xto running v vs1 = v vs2 = v vsint = 3v (battery) clk disabled 17, 18, 27 i s_idle 260 a b xto running v vs2 = v vsint = 5v (car) clk disabled 17, 27 i s_idle 350 a b 1.4 system start-up time from off mode to idle mode including reset and xto start-up (see figure 12-4 on page 46 ) xtal: c m = 5 ff, c 0 = 1.8 pf, r m = 15 ? t pwr_on_irq_1 0.3 ms c 1.5 rx start-up time from idle mode to receiving mode n bit-check = 3 baud rate = 20 kbaud, br_range_3 (see figure 14-1 on page 54 and figure 14-2 on page 55 ) t startup_pll + t startup_sig_proc + t bit-check 1.39 ms a 1.6 tx start-up time from idle mode to tx mode (see figure 14-10 on page 62 ) t startup 0.4 ms a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 73 4829c?rke?09/05 ATA5823/ata5824 2 receiver/rx mode 2.1 supply current rx mode f rf = 433.92 mhz and f rf = 315 mhz 17, 18, 27 i s_rx 10.5 ma a f rf = 868.3 mhz 17, 18, 27 i s_rx 10.3 ma a 2.2 supply current rx polling mode t sleep = 49.45 ms x sleep = 8, sleep = 5 baud rate = 20 kbaud fsk, clk disabled 17, 18, 27 i s_poll 484 a c 2.3 input sensitivity fsk f rf = 433.92 mhz fsk deviation f dev = 19.5 khz limits according to table 14-3 on page 60 , ber = 10 -3 t amb = 25c baud rate 20 kbaud (4) s ref_fsk ?103.5 ?105.5 ?107.0 dbm b baud rate 2.4 kbaud (4) s ref_fsk ?107.0 ?109.0 ?110.5 dbm b 2.4 input sensitivity ask f rf = 433.92 mhz ask 100% level of carrier, limits according to table 14-3 on page 60 , ber = 10 -3 t amb = 25c baud rate 10 kbaud (4) p ref_ask ?109.5 ?111.5 ?113.0 dbm b baud rate 2.4 kbaud (4) p ref_ask ?113.5 ?115.5 ?117.0 dbm b 2.5 sensitivity change at f rf = 315 mhz f rf = 868.3 mhz compared to f rf = 433.92 mhz f rf = 433.92 mhz to f rf = 315 mhz f rf = 433.92 mhz to f rf = 868.3 mhz s = s ref_ask + ? s ref1 s = s ref_fsk + ? s ref1 (4) ? s ref1 ?1.0 +2.7 db b 2.6 sensitivity change versus temperature, supply voltage and frequency offset fsk f dev = 19.5 khz ? f offset 75 khz ask 100% ? f offset 75 khz s = s ref_ask + ? s ref1 + ? s ref2 s = s ref_fsk + ? s ref1 + ? s ref2 (4) ? s ref2 +4.5 ?1.5 b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 74 4829c?rke?09/05 ATA5823/ata5824 2.7 rssi output dynamic range (4), 36 d rssi 70 db a lower level of range f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz (4), 36 p rfin_low ?116 ?115 ?112 dbm dbm dbm a upper level of range f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz (4), 36 p rfin_high ?46 ?45 ?42 dbm dbm dbm a gain (4), 36 5.5 8.0 10.5 mv/db a output voltage range (4), 36 ov rssi 350 1100 mv a 2.8 output resistance rssi pin rx mode tx mode 36 r rssi 8 32 10 40 12.5 50 k ? c 2.9 maximum frequency offset in fsk mode maximum frequency difference of f rf between receiver and transmitter in fsk mode (f rf is the center frequency of the fsk signal with f dev = 19.5 khz) p rf_in +10 dbm p rf_in p rfin_high (see figure 7-2 on page 12 ) (4) ? f offset1 ? f offset2 ?69 ?75 +69 +75 khz b 2.10 supported fsk frequency deviation with up to 2 db loss of sensitivity. note that the tolerable frequency offset is for f dev = 28 khz, 8.5 khz lower than for f dev = 19.5 khz hence ? f offset2 = 66.5 khz (4) f dev 14 19.5 28 khz b 2.11 system noise figure f rf = 315 mhz (4) nf 5.5 db b f rf = 433.92 mhz (4) nf 6.5 db b f rf = 868.3 mhz (4) nf 9.7 db b 2.12 intermediate frequency f rf = 315 mhz f if 227 khz a f rf = 433.92 mhz f if 223 khz a f rf = 868.3 mhz f if 226 khz a 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 75 4829c?rke?09/05 ATA5823/ata5824 2.13 system bandwidth this value is for information only! note that for crystal and system frequency offset calculations, ? f offset must be used. (4) sbw 220 khz a 2.14 system out-band 2 nd -order input intercept point with respect to f if ? f meas1 = 1.800 mhz ? f meas2 = 2.026 mhz f if = ? f meas2 ? ? f meas1 (4) iip2 +50 dbm c 2.15 system outband 3 rd -order input intercept point ? f meas1 = 1.8 mhz ? f meas2 = 3.6 mhz f rf = 315 mhz (4) iip3 ?22 dbm c f rf = 433.92 mhz (4) iip3 ?21 dbm c f rf = 868.3 mhz (4) iip3 ?17 dbm c 2.16 system outband input 1 db compression point ? f meas1 = 10 mhz f rf = 315 mhz this values are for information only, for blocking behavior see figure 7-3 on page 15 to figure 7-7 on page 17 (4) i1dbcp ?31 dbm c f rf = 433.92 mhz (4) i1dbcp ?30 dbm c f rf = 868.3 mhz (4) i1dbcp ?27 dbm c 2.17 lna input impedance f rf = 315 mhz 4 z in_lna (44 ? j233) ? c f rf = 433.92 mhz 4 z in_lna (32 ? j169) ? c f rf = 868.3 mhz 4 z in_lna (21 ? j78) ? c 2.18 allowable peak rf input level, ask and fsk ber < 10 -3 , ask: 100% (4) p in_max +10 ?10 dbm c fsk: f dev = 19.5 khz (4) p in_max +10 ?10 dbm c 2.19 lo spurious at lna_in f < 1 ghz (4) ?57 dbm c f >1 ghz (4) ?47 dbm c f rf = 315 mhz (4) ?100 dbm c f rf = 433.92 mhz (4) ?98 dbm c f rf = 868.3 mhz (4) ?85 dbm c 2.20 image rejection within the complete image band f rf = 315 mhz (4) 25 30 db a f rf = 433.92 mhz (4) 25 30 db a f rf = 868.3 mhz (4) 20 25 db a 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 76 4829c?rke?09/05 ATA5823/ata5824 2.21 useful signal to interferer ratio peak level of useful signal to peak level of interferer for ber < 10 -3 with any modulation scheme of interferer. fsk br_ranges 0, 1, 2 (4) snr fsk0-2 23dbb fsk br_range_3 (4) snr fsk3 46dbb ask (p rf < p rfin_high )(4)snr ask 10 12 db b 2.22 maximum frequency offset in ask mode maximum frequency difference of f rf between receiver and transmitter in ask mode p rf_in +10 dbm p rf_in p rf_in_high ? f offset1 ? f offset2 ?79 ?85 +79 +85 khz b 2.23 blocking according to etsi regulations, the sensitivity (ber = 10 -3 ) is reduced by 3 db if a continuous wave blocking signal at ? f is ? p block higher than the useful signal level (baud rate = 20 kbaud, fsk, f dev 19.5 khz, manchester code) f rf = 315 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5.0 mhz ? f 10.0 mhz blocking behavior see figure 7-3 to figure 7-5 on page 15 (4) ? p block 55 57 60 66 73 dbc c f rf = 433.92 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5.0 mhz ? f 10.0 mhz blocking behavior see figure 7-3 to figure 7-5 on page 15 (4) ? p block 54 56 59 65 67 dbc c 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 77 4829c?rke?09/05 ATA5823/ata5824 f rf = 868.3 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5.0 mhz ? f 10.0 mhz blocking behavior see figure 7-3 to figure 7-5 on page 15 (4) ? p block 49 52 56 64 67 dbc c 2.24 cdem capacitor connected to pin 37 (cdem) 37 ?5% 15 +5% nf d 3 power amplifier/tx mode 3.1 supply current tx mode power amplifier off f rf = 868.3 mhz 17,18, 27 i s_tx_paoff 6.50 ma a f rf = 433.92 mhz and f rf = 315 mhz 17,18, 27 i s_tx_paoff 6.95 ma a 3.2 output power 1 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = gnd f rf = 315 mhz r r_pwr = 56 k ? r lopt = 2.5 k ? f rf = 433.92 mhz r r_pwr = 56 k ? r lopt = 2.3 k ? f rf = 868.3 mhz r r_pwr = 30 k ? r lopt = 1.3 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref1 ?2.5 0 +2.5 dbm b 3.3 supply current tx mode power amplifier on 1 0 dbm pa on/0 dbm f rf = 315 mhz 17, 18, 27 i s_tx_paon1 8.5 ma b f rf = 433.92 mhz 17, 18, 27 i s_tx_paon1 8.6 ma b f rf = 868.3 mhz 17, 18, 27 i s_tx_paon1 9.6 ma b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 78 4829c?rke?09/05 ATA5823/ata5824 3.4 output power 2 v vs1 = v vs2 = 3 v t amb = 25c v pwr_h = gnd f rf = 315 mhz r r_pwr = 30 k ? r lopt = 1.0 k ? f rf = 433.92 mhz r r_pwr = 27 k ? r lopt = 1.1 k ? f rf = 868.3 mhz r r_pwr = 16 k ? r lopt = 0.5 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref2 3.5 5.0 6.5 dbm b 3.5 supply current tx mode power amplifier on 2 5 dbm pa on/5 dbm f rf = 315 mhz 17, 18, 27 i s_tx_paon2 10.3 ma b f rf = 433.92 mhz 17, 18, 27 i s_tx_paon2 10.5 ma b f rf = 868.3 mhz 17, 18, 27 i s_tx_paon2 11.2 ma b 3.6 output power 3 v vs1 = v vs2 = 3 v t amb = 25c v pwr_h = avcc f rf = 315 mhz r r_pwr = 30 k ? r lopt = 0.38 k ? f rf = 433.92 mhz r r_pwr = 27 k ? r lopt = 0.36 k ? f rf = 868.3 mhz r r_pwr = 20 k ? r lopt = 0.22 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref3 8.5 10 11.5 dbm b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 79 4829c?rke?09/05 ATA5823/ata5824 3.7 supply current tx mode power amplifier on 3 10 dbm pa on/10dbm f rf = 315 mhz 17, 18, 27 i s_tx_paon3 15.7 ma b f rf = 433.92 mhz 17, 18, 27 i s_tx_paon3 15.8 ma b f rf = 868.3 mhz 17, 18, 27 i s_tx_paon3 17.3 ma b 3.8 output power variation for full temperature and supply voltage range t amb = ?40c to +105c p out = p refx + ? p ref x = 1, 2 or 3 v vs1 = v vs2 = 3.0v (10) ? p ref ?0.8 ?1.5 db b v vs1 = v vs2 = 2.7v (10) ? p ref ?2.5 db b v vs1 = v vs2 = 2.4v (10) ? p ref ?3.5 db c v vs1 = v vs2 = 2.15v (10) ? p ref ?4.5 db b 3.9 impedance rf_out in rx mode f rf = 315 mhz 10 z rf_out_rx (36 ? j502) ? c f rf = 433.92 mhz 10 z rf_out_rx (19 ? j366) ? c f rf = 868.3 mhz 10 z rf_out_rx (2.8 ? j141) ? c 3.10 noise floor power amplifier at 10 mhz/at 5 dbm f rf = 868.3 mhz (10) l tx10m ?125 dbc/hz c f rf = 433.92 mhz (10) l tx10m ?126 dbc/hz c f rf = 315 mhz (10) l tx10m ?128 dbc/hz c 3.11 ask modulation rate this corresponds to 10 kbaud manchester coding and 20 kbaud nrz coding f data_ask 110khzc 4 full-duplex mode f rf = 315 mhz and f rf = 433.92 mhz 4.1 supply current fd mode 1 p out = ?10 dbm r r_pwr = 22 k ? pwset=13 load optimized for +5 dbm! 17,18, 27 i s_fd1 11.9 ma b 4.2 supply current fd mode 2 p out = ?5 dbm r r_pwr = 22 k ? pwset=20 load optimized for +5 dbm! 17,18, 27 i s_fd2 12.5 ma b 4.3 supply current fd mode 3 p out = 0 dbm r r_pwr = 22 k ? pwset=27 load optimized for +5 dbm! 17,18, 27 i s_fd3 13.7 ma b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 80 4829c?rke?09/05 ATA5823/ata5824 4.4 supply current fd mode 4 p out = 5 dbm r r_pwr = 22 k ? pwset=31 load optimized for +5 dbm! 17,18, 27 i s_fd4 15.2 ma b 4.5 input sensitivity fd mode v vs1 = v vs2 = 3 v t amb = 25c, per = 5% p(rf out @rf in ): ?30 dbm ?35 dbm ?40 dbm ?45 dbm ?50 dbm baud rate 5 kbaud (4) s refrx_fd ?88.5 ?93.5 ?97.5 ?100.5 ?101.5 ?91 ?96 ?100 ?103 ?104 ?92.5 ?97.5 ?101.5 ?104.5 ?105.5 dbm b 4.6 sensitivity change fd mode v vs1 = v vs2 = 2.15v to 3.6v coupling phase 0 to 360 t amb = ?40c to +105c frequency offset max. 50 khz s = s refrx_fd + ? s refrx_fd (4) ? s refrx_fd ?3 0 5 db b 4.7 output power fd1 v vs1 = v vs2 = 3v t amb = 25c r r_pwr = 22 k ? pwset = 13 load optimized for +5 dbm! (10) p reftx_fd1 ?12.5 ?10 ?7.5 dbm b 4.8 output power fd1 variation for full temperature range v vs1 = v vs2 = 3v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 13 p = p reftx_fd1 + ? p reftx_fd1 (10) ? p reftx_fd1 ?3 ?1.5 2 db b 4.9 output power fd1 variation for full temperature and supply voltage range v vs1 = v vs2 = 2.15v to 3.6v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 13 p = p reftx_fd1 + ? p reftx_fd1 (10) ? p reftx_fd1 ?5.5 2.5 db b 4.10 output power fd2 v vs1 = v vs2 = 3v t amb = 25c r r_pwr = 22 k ? pwset = 20 load optimized for +5 dbm! (10) p reftx_fd2 ?7.5 ?5 ?2.5 dbm b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 81 4829c?rke?09/05 ATA5823/ata5824 4.11 output power fd2 variation for full temperature range v vs1 = v vs2 = 3v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 20 p = p reftx_fd2 + ? p reftx_fd2 (10) ? p reftx_fd2 ?2.5 ?1.2 1 db b 4.12 output power fd2 variation for full temperature and supply voltage range v vs1 = v vs2 = 2.15v to 3.6v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 20 p = p reftx_fd2 + ? p reftx_fd2 (10) ? p reftx_fd2 ?4.5 1.5 db b 4.13 output power fd3 v vs1 = v vs2 = 3v t amb = 25c r r_pwr = 22 k ? pwset = 27 load optimized for +5 dbm! (10) p reftx_fd3 ?2.5 0 2.5 dbm b 4.14 output power fd3 variation for full temperature range v vs1 = v vs2 = 3v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 27 p = p reftx_fd3 + ? p reftx_fd3 (10) ? p reftx_fd3 ?1.5 ?0.8 0.5 db b 4.15 output power fd3 variation for full temperature and supply voltage range v vs1 = v vs2 = 2.15v to 3.6v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 27 p = p reftx_fd3 + ? p reftx_fd3 (10) ? p reftx_fd3 ?4.5 1 db b 4.16 output power fd4 v vs1 = v vs2 = 3v t amb = 25c r r_pwr = 22 k ? pwset = 31 load optimized for +5 dbm! (10) p reftx_fd4 3.5 5 6.5 dbm b 4.17 output power fd4 variation for full temperature range v vs1 = v vs2 = 3v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 31 p = p reftx_fd4 + ? p reftx_fd4 (10) ? p reftx_fd4 ?1.5 ?0.8 0.5 db b 4.18 output power fd4 variation for full temperature and supply voltage range v vs1 = v vs2 = 2.15v to 3.6v t amb = ?40c to 105c r r_pwr = 22 k ? pwset = 31 p = p reftx_fd4 + ? p reftx_fd4 (10) ? p reftx_fd4 ?4.5 1 db b 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 82 4829c?rke?09/05 ATA5823/ata5824 5xto 5.1 pulling xto due to xto, c l1 and c l2 tolerances pulling at nominal temperature and supply voltage f xtal = resonant frequency of the xtal c 0 1.0 pf r m 120 ? 24, 25 c m 7.0 ff c m 14 ff ? f xto1 ?50 ?100 f xtal +50 +100 ppm a 5.2 transconductance xto at start at start-up, after start-up the amplitude is regulated to v ppxtal 24, 25 g m, xto 19 ms b 5.3 xto start-up time c 0 2.2 pf c m < 14 ff r m 120 ? 24, 25 t pwr_on_irq_1 300 800 s a 5.4 maximum c 0 of xtal required for stable operation with internal load capacitors 24, 25 c 0max 3.8 pf d 5.5 internal capacitors c l1 and c l2 24, 25 c l1 , c l2 14.8 18 pf 21.2 pf b 5.6 pulling of radio frequency f rf due to xto, c l1 and c l2 versus temperature and supply changes 1.0 pf c 0 2.2 pf c m = 14 ff r m 120 ? pll adjusted with freq at nominal temperature and supply voltage 4, 10 ? f xto2 ?2 +2 ppm c 5.7 amplitude xtal after start-up c m = 5 ff, c 0 = 1.8 pf r m = 15 ? v(xtal1, xtal2) peak-to-peak value 24, 25 v ppxtal 700 mvpp c v(xtal1) peak-to-peak value 24 v ppxtal 350 mvpp c 5.8 real part of xto impedance at start-up c 0 2.2 pf, small signal start impedance, this value is important for crystal oscillator startup 24, 25 re xto ?2000 ?1500 ? b 5.9 maximum series resistance r m of xtal after start-up c 0 2.2 pf c m 14 ff 24, 25 r m_max 15 120 ? b 5.10 nominal xtal load resonant frequency f rf = 868.3 mhz f rf = 433.92 mhz f rf = 315 mhz 24, 25 f xtal 13.41191 13.25311 12.73193 mhz mhz mhz d 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 83 4829c?rke?09/05 ATA5823/ata5824 5.11 external clk frequency 30 f clk mhz d f rf = 868.3 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.471 mhz d f rf = 433.92 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.418 mhz d f rf = 315 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.244 mhz d 5.12 dc voltage after start-up v dc (xtal1, xtal2) xto running (idle mode, rx mode and tx mode) 24, 25 v dcxto ?150 ?30 me c 6 programmable internal resistor setpwr 6.1 setpwr in tx- and fd mode setpwr = 800 ? + (31 ? pwset) 3 k ? pwset = 16 (see table 12-25 on page 43 ) 19 setpwr 45.8 k ? b 6.2 tolerance of setpwr versus temperature and supply voltage range 19 setpwrtol ?20% 500 ? +20% 500 ? b 7 synthesizer 7.1 spurious tx mode at f clk , clk enabled f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp tx < ?75 < ?75 ?74 dbc a a b at f xto f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp tx ?73 ?70 ?65 dbc a 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). f clk f xto 3 ---------- - = 84 4829c?rke?09/05 ATA5823/ata5824 7.2 spurious rx mode at f clk , clk enabled f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp rx < ?75 < ?75 < ?75 dbc a a b at f xto f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp rx ?74 ?72 ?68 dbc a 7.3 in loop phase noise tx mode measured at 20 khz distance to carrier f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l tx20k ?83 ?78 ?73 dbc/hz a 7.4 phase noise at 1m rx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l rx1m ?121 ?120 ?113 dbc/hz a 7.5 phase noise at 1m tx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l tx1m ?113 ?111 ?108 dbc/hz a 7.6 phase noise at 10m rx mode noise floor l rx10m < ?132 dbc/hz b 7.7 loop bandwidth pll tx mode frequency where the absolute value loop gain is equal to 1 f loop_pll 70 khz b 7.8 frequency deviation tx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz f dev_tx 18.65 19.41 19.64 khz d 7.9 frequency resolution f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz 4, 10 ? f step_pll 777.1 808.9 818.6 hz d 7.10 fsk modulation rate this corresponds to 20 kbaud manchester coding and 40 kbaud nrz coding f data_fsk 120khzb 8 rx/tx switch 8.1 impedance rx mode rx mode, pin 38 with short connection to gnd , f rf = 0 hz (dc) 39 z switch_rx 23000 ? a f rf = 315 mhz 39 z switch_rx (11.3 ? j214) ? c f rf = 433.92 mhz 39 z switch_rx (10.3 ? j153) ? c f rf = 868.3 mhz 39 z switch_rx (8.9 ? j73) ? c 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). 85 4829c?rke?09/05 ATA5823/ata5824 8.2 impedance tx mode tx mode, pin 38 with short connection to gnd , f rf = 0hz (dc) 39 z switch_tx 5 ? a f rf = 315 mhz 39 z switch_tx (4.8 + j3.2) ? c f rf = 433.92 mhz 39 z switch_tx (4.5 + j4.3) ? c f rf = 868.3 mhz 39 z switch_tx (5 + j9) ? c 9 microcontroller interface 9.1 voltage range for microcontroller interface 27, 28, 29, 30, 31, 32, 33, 34, 35 2.15 5.25 v a 9.2 clk output rise and fall time f clk < 4.5 mhz c l = 10 pf c l = load capacitance on pin clk 2.15v v vsint 5.25v 20% to 80% v vsint 30 t rise t fall 20 20 30 30 ns ns b b 9.3 current consumption of the microcontroller interface clk enabled clk disabled c l = load capacitance on pin clk (all interface pins, except pin clk, are in stable conditions and unloaded) 27 i vsint < 10 a b 9.4 internal equivalent capacitance used for current calculation 30, 27 c clk 8pfb 17. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 = v vs2 = v vsint = 3v and t amb = 25c, f rf = 433.92 mhz (battery application) unless ot herwise specified. details about current consumption, timing and digital pin proper ties can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 7-1 on page 11 with component values according to table 7-2 on page 12 (rf in ) and rf_out matched to 50 ? according to figure 7-12 on page 22 with component values according to table 7-7 on page 22 (rf out ). i vsint c clk c l + () v vsint f xto 3 --------------------------------------------------------------------------- - = 86 4829c?rke?09/05 ATA5823/ata5824 18. electrical characterist ic: battery application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v typical values at v vs1 = v vs2 = 3v and t amb = 25c. application according to figure 3-1 on page 6 or figure 5-1 on page 8 . f rf = 315.0 mhz/ 433.92 mhz/868.3 mhz unless otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pi n symbol min. typ. max. unit type* 10 battery application 10.1 supported voltage range (every mode except high power tx mode) battery application pwr_h = gnd 17, 18 v vs1 , v vs2 2.15 3.6 v a 10.2 supported voltage range (high power tx mode) battery application pwr_h = avcc 17, 18 v vs1 , v vs2 2.7 3.6 v a 10.3 supply voltage for microcontroller interface 27 v vsint 2.15 5.25 v a 10.4 supply current off mode v vs1,2 = v vsint 3.6vi s _off = i off_vs1,2 + i off_vsint 17,18, 27 i s_off 2 350 na a 10.5 current in idle mode on pin vs1 and vs2 v vs1 = v vs2 3v clk enabled clk disabled 17, 18 i idle_vs1, 2 330 270 570 490 a a a b 10.6 supply current idle mode clk enabled 17, 18, 27 i s_idle i s_idle = i idle_vs1,2 + i vsint 10.7 current in rx mode on pin vs1and vs2 v vs1 = v vs2 3v 17, 18 i rx_vs1, 2 10.5 14 ma a 10.8 supply current rx mode clk enabled 17, 18, 27 i s_rx i s_rx = i rx_vs1, 2 + i vsint 10.9 current during t startup_pll on pin vs1 and vs2 v vs1 = v vs2 3v 17, 18 i startup_pll_vs1, 2 8.8 11.5 ma c 10.10 current in rx polling mode on pin vs1 and vs2 10.11 supply current rx polling mode 17, 18, 27 i s_poll i poll = i p + i vsint *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter i idle_vs1,2 or i rx_vs1,2 or i startup_pll_vs1,2 or i tx_vs1,2 or i fd1,2_vs1,2 vs1 vs2 i poll i idle_vs1,2 t sleep i startup_pll_vs1,2 t startup_pll i rx_vs1,2 t startup_sig_proc t bit check + () + + t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------- = 87 4829c?rke?09/05 ATA5823/ata5824 10.12 current in tx mode on pin vs1 and vs2 v vs1 = v vs2 3v 315 mhz/5 dbm 315 mhz/10 dbm 433.92 mhz/5 dbm 433.92 mhz/10 dbm 868.3 mhz/5 dbm 868.3 mhz/10 dbm 17, 18 i tx_vs1_vs2 10.3 15.7 10.5 15.8 11.2 17.3 13.4 20.5 13.5 20.5 14.5 22.5 ma b 10.13 supply current tx mode 17, 18, 27 i s_tx i s_tx = i tx_vs1_vs 2 + i vsint 11 full-duplex mode 11.1 current in full-duplex mode p out = ?10 dbm v vs1 = v vs2 3v r r_pwr = 22 k ? pwset = 13 load optimized for +5 dbm! 17, 18, 27 i fd1_vs1_vs2 11.9 16.5 ma b 11.2 current in full-duplex mode p out = ?5 dbm v vs1 = v vs2 3v r r_pwr = 22 k ? pwset= 20 load optimized for +5 dbm! 17, 18, 27 i fd2_vs1_vs2 12.5 17.4 ma b 11.3 current in full-duplex mode p out = 0 dbm v vs1 = v vs2 3v r r_pwr = 22 k ? pwset = 27 load optimized for +5 dbm! 17, 18, 27 i fd3_vs1_vs2 13.7 18.3 ma b 11.4 supply current full-duplex mode 17, 18, 27 i s_fd i s_fd = i fd1,2,3_vs1_vs2 + i vsint 18. electrical characteristic: ba ttery application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v typical values at v vs1 = v vs2 = 3v and t amb = 25c. application according to figure 3-1 on page 6 or figure 5-1 on page 8 . f rf = 315.0 mhz/ 433.92 mhz/868.3 mhz unless otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 88 4829c?rke?09/05 ATA5823/ata5824 19. electrical characteri stics: car application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v. typical values at v vs2 = 5v and t amb = 25c. application according to figure 4-1 on page 7 . f rf = 315.0 mhz/433.92 mhz/868.3 mhz unless otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pi n symbol min. typ. max. unit type* 12 car application 12.1 supported voltage range car application 17 v vs2 4.4 5.6 v a 12.2 supply voltage for microcontroller- interface 27 v vsint 2.15 5.25 v a 12.3 supply current off mode v vs2 = v vsint 5.25vi s _off = i off_vs2 + i off_vsint 17,27 i s_off 0.5 6 a a 12.4 current in idle mode on pin vs2 v vs2 5v clk enabled clk disabled 17 i idle_vs2 430 360 600 520 a a a b 12.5 supply current idle mode clk enabled 17, 27 i s_idle i s_idle = i idle_vs2 + i vsint 12.6 current in rx mode on pin vs2 v vs2 = 5v 17 i rx_vs2 10.8 14.5 ma b 12.7 supply current rx mode clk enabled 17, 27 i s_rx i s_rx = i rx_vs2 + i vsint 12.8 current during t startup_pll on pin vs2 v vs2 = 5v 17 i startup_pll_vs2 9.1 12 ma c 12.9 current in rx polling mode on pin vs2 12.10 supply current rx polling mode 17, 27 i s_poll i s_poll = i poll + i vsint 12.11 current in tx mode on pin vs2 v vs2 = 5v 315 mhz/5dbm 315 mhz/10dbm 433.92 mhz/5dbm 433.92 mhz/10dbm 868.3 mhz/5dbm 868.3 mhz/10dbm 17 i tx_vs2 10.7 16.2 10.9 16.3 11.6 17.8 13.9 21.0 14.0 21.0 15.0 23.0 ma b 12.12 supply current tx mode 17, 27 i s_tx i s_tx = i tx_vs2 + i vsint *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter vs2 i idle_vs2 or i rx_vs2 or i startup_pll_vs2 or i tx_vs2 or i fd3,4_vs2 i poll "" i idle_vs2 t sleep i startup_pll_vs2 t startup_pll i rx_vs2 t startup_sig_proc t bit check + () + + t sleep t startup_pll t startup_sig_proc t bit check ++ + ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------- = 89 4829c?rke?09/05 ATA5823/ata5824 13 full-duplex mode 13.1 current in full-duplex mode p out = ?5 dbm v vs2 = 5v r r_pwr = 22 k ? pwset = 19 load optimized for +5 dbm! 17, 27 i fd4_vs2 12.7 16.9 ma b 13.2 current in full-duplex mode p out = 0 dbm v vs2 = 5v r r_pwr = 22 k ? pwset = 26 load optimized for +5 dbm! 17, 27 i fd5_vs2 13.8 18.4 ma b 13.3 current in full-duplex mode p out = 5 dbm v vs2 = 5v r r_pwr = 22 k ? pwset = 31 load optimized for +5 dbm! 17, 27 i fd6_vs2 15.6 20.8 ma b 13.4 supply current full-duplex mode 17, 27 i s_fd i s_fd = i fd4,5,6_vs2 + i vsint 19. electrical characteristics: car application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v. typical values at v vs2 = 5v and t amb = 25c. application according to figure 4-1 on page 7 . f rf = 315.0 mhz/433.92 mhz/868.3 mhz unless otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter 90 4829c?rke?09/05 ATA5823/ata5824 20. digital timing characteristics all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = v vsint = 4.4v to 5.25v (car application), typical values at v vs1 = v vs2 = v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* 14 basic clock cycle of the digital circuitry 14.1 basic clock cycle t dclk 16/f xto 16/f xto s a 14.2 extended basic clock cycle xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 t xdclk 8 4 2 1 t dclk 16 8 4 2 t dclk 8 4 2 1 t dclk 16 8 4 2 t dclk s s a a 15 rx mode/rx polling mode 15.1 sleep time sleep and xsleep are defined in control register 4 t sleep sleep x sleep 1024 t dclk sleep x sleep 1024 t dclk ms a 15.2 start-up pll rx mode from idle mode t startup_pll 798.5 t dclk 798.5 t dclk s a 15.3 start-up signal processing br_range_0 br_range_1 br_range_2 br_range_3 t startup_sig_proc 930 546 354 258 t dclk 930 546 354 258 t dclk a 15.4 time for bit-check average time during polling. no rf signal applied. f signal = 1/(2 t ee ) signal data rate manchester (lim_min and lim_max up to 50% of t ee , see figure 14-3 on page 55 ) bit-check time for a valid input signal f signal n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit_check 3/f signal 6/f signal 9/f signal 1/f signal 3.5/f signal 6.5/f signal 9.5/f signal ms c *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 91 4829c?rke?09/05 ATA5823/ata5824 15.5 baud-rate range br_range = br_range0 br_range1 br_range2 br_range3 br_range 1.0 2.0 4.0 8.0 2.5 5.0 10.0 20.0 kbaud a 15.6 minimum time period between edges at pin sdo_tmdo in rx transparent mode xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 31 t data_min 10 t xdclk s a 15.7 edge-to-edge time period of the data signal for full sensitivity in rx mode br_range_0 br_range_1 br_range_2 br_range_3 t data 200 100 50 25 500 250 125 62.5 s b 16 tx mode 16.1 start-up time from idle mode t startup 331.5 t dclk 331.5 t dclk s a 17 configuration of the transceive r with 4-wire serial interface 17.1 cs set-up time to rising edge of sck 33, 35 t cs_setup 1.5 t dclk s a 17.2 sck cycle time 33 t cycle 2sa 17.3 sdi_tmdi set-up time to rising edge of sck 32, 33 t setup 250 ns c 17.4 sdi_tmdi hold time from rising edge of sck 32, 33 t hold 250 ns c 17.5 sdo_tmdo enable time from rising edge of cs 31, 35 t out_enable 250 ns c 17.6 sdo_tmdo output delay from falling edge of sck c l = 10 pf 31, 35 t out_delay 250 ns c 17.7 sdo_tmdo disable time from falling edge of cs 31, 33 t out_disable 250 ns c 17.8 cs disable time period 35 t cs_disable 1.5 t dclk s a 17.9 time period sck low to cs high 33, 35 t sck_setup1 250 ns c 20. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = v vsint = 4.4v to 5.25v (car application), typical values at v vs1 = v vs2 = v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 92 4829c?rke?09/05 ATA5823/ata5824 17.10 time period sck low to cs low 33, 35 t sck_setup2 250 ns c 17.11 time period cs low to sck high 33, 35 t sck_hold 250 ns c 18 start time push butto n n_pwr_on and pwr_on timing of wake-up via pwr_on or n_pwr_on 18.1 pwr_on high to positive edge on pin irq ( figure 12-4 on page 46 ) from off mode to idle mode, applications according to figure 3-1 on page 6 , figure 4-1 on page 7 , figure 5-1 on page 8 and figure 6-1 on page 9 xtal: c m < 14 ff (typ. 5 ff) c 0 < 2.2 pf (typ. 1.8 pf) r m 120 ? (typ. 15 ? ) battery application c 1 = c 2 = c 3 = 68 nf c 5 = c 7 = 10 nf car application c 1 = c 3 = c 4 = 68 nf c 2 = 2.2 f c 5 = 10 nf 29, 40 t pwr_on_irq_1 0.3 0.45 0.8 1.3 ms b 18.2 pwr_on high to positive edge on pin irq ( figure 12-4 on page 46 ) from every mode except off mode 29, 40 t pwr_on_irq_2 2 t dclk s a 20. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = v vsint = 4.4v to 5.25v (car application), typical values at v vs1 = v vs2 = v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 93 4829c?rke?09/05 ATA5823/ata5824 18.3 n_pwr_on low to positive edge on pin irq ( figure 12-2 on page 44 ) from off mode to idle mode, applications according to figure 3-1 on page 6 , figure 4-1 on page 7 , figure 5-1 on page 8 and figure 6-1 on page 9 xtal: c m < 14 ff (typ 5 ff) c 0 < 2.2 pf (typ 1.8 pf) r m 120 ? (typ 15 ? ) battery application c 1 = c 2 = 68 nf c 3 = c 4 = 68 nf c 5 = 10 nf car application c 1 = c 4 = 68 nf c 2 = c 3 = 2.2 f c 5 = 10 nf 29, 45 t n_pwr_on_irq 0.3 0.45 0.8 1.3 ms b 18.4 push button debounce time every mode except off mode 29, 45 t debounce 8195 t dclk 8195 t dclk s a 19 full-duplex mode 19.1 start-up pll in full-duplex mode from idle mode t startup_pll_fd 798.5 t dclk 798.5 t dclk s a 19.2 start-up signal processing fd mode data rate is fixed for full-duplex operation t startup_sig_proc_fd 546 t dclk 546 t dclk s a 19.3 time per information bit in full-duplex mode data rate is fixed for full-duplex operation t bit_fd 168 t dclk 168 t dclk s a 19.4 switch off delay time from last transmitted bit to switch of the power amplifier t delay 168 t dclk 168 t dclk s a 19.5 synchronization time time after startbit detection to begin of payload data transmission t sync 24 t bit-fd 24 t bit-fd s a 20. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = v vsint = 4.4v to 5.25v (car application), typical values at v vs1 = v vs2 = v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 94 4829c?rke?09/05 ATA5823/ata5824 21. digital port characteristics all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v (battery application) and v vs2 = 4.4v to 5.25v (car application) typical values at v vs1 = v vs2 = 3v (battery application) and t amb = 25c unless otherwise specified. v vsint = 2.15v to 5.25v can be used independent from v vs1 and v vs2 in the case the microcontroller uses an different supply voltage. no. parameters test conditions pin symbol min. typ. max. unit type* 20 digital ports 20.1 cs input - low level input voltage v vsint = 2.15v to 5.25v 35 v il 0.2 v vsint va - high level input voltage v vsint = 2.15v to 5.25v 35 v ih 0.8 v vsint va 20.2 sck input - low level input voltage v vsint = 2.15v to 5.25v 33 v il 0.2 v vsint va - high level input voltage v vsint = 2.15v to 5.25v 33 v ih 0.8 v vsint va 20.3 sdi_tmdi input - low level input voltage v vsint = 2.15v to 5.25v 32 v il 0.2 v vsint va - high level input voltage v vsint = 2.15v to 5.25v 32 v ih 0.8 v vsint va 20.4 test1 input test1 input must always be directly connected to gnd 20 0 0 v 20.5 test2 input test2 input must always be direct connected to gnd 23 0 0 v 20.6 pwr_on input - low level input voltage v vsint = 2.15v to 5.25v 40 v il 0.2 v vsint va - high level input voltage v vsint = 2.15v to 5.25v 40 v ih 0.8 v vsint va 20.7 n_pwr_on input - low level input voltage v vsint = 2.15v to 5.25v internal pull-up resistor of 50 k ? 20% 45 v il 0.2 v vsint va - high level input voltage v vsint = 2.15v to 5.25v internal pull-up resistor of 50 k ? 20% 45 v ih 0.8 v vsint va 20.8 cs_pol input -low level input voltage 22 v il 0.2 v dvcc va - high level input voltage 22 v ih 0.8 v dvcc v dvcc va 20.9 sck_pol input - low level input voltage 43 v il 0.2 v dvcc va - high level input voltage 43 v ih 0.8 v dvcc v dvcc va 20.10 sck_pha input - low level input voltage 44 v il 0.2 v dvcc va - high level input voltage 44 v ih 0.8 v dvcc v dvcc va *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 95 4829c?rke?09/05 ATA5823/ata5824 20.11 433_n868 input - low level input voltage 6v il 0.25 v a - high level input voltage 6 v ih 1.7 avcc v a 20.12 pwr_h input - low level input voltage 9v il 0.25 v a - high level input voltage 9 v ih 1.7 avcc v a 20.13 sdo_tmdo output - saturation voltage low v vsint = 2.15v to 5.25v i sdo_tmdo = 250 a 31 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i sdo_tmdo = ?250 a 31 v oh v vsint ? 0.4 v vsint ? 0.15 vb 20.14 irq output - saturation voltage low v vsint = 2.15v to 5.25v i irq = 250 a 29 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i irq = ?250 a 29 v oh v vsint ? 0.4 v vsint ? 0.15 vb 20.15 clk output - saturation voltage low v vsint = 2.15v to 5.25v i clk = 100 a internal series resistor of 1 k ? for spurious reduction in pll 30 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i clk = ?100 a internal series resistor of 1 k ? for spurious reduction in pll 30 v oh v vsint ? 0.4 v vsint ? 0.15 vb 20.16 pout output - saturation voltage low v vsint = 2.15v to 5.25v i pout = 250 a 28 v ol 0.15 0.4 v b pout output - saturation voltage low v vsint = 5v i pout = 1000 a 28 v ol 0.4 0.6 v b pout output - saturation voltage high v vsint = 2.15v to 5.25v i pout = ?1500 a 28 v oh v vsint ? 0.4 v vsint ? 0.15 vb 20.17 rx_active output - saturation voltage low i rx_active = 25 a 46 v ol 0.25 0.4 v b rx_active output - saturation voltage high i rx_active = ?1500 a 46 v oh v avcc ? 0.5 v avcc ? 0.15 vb 20.18 test3 output test3 output must always be directly connected to gnd 34 0 0 v 21. digital port characteristics (continued) all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v (battery application) and v vs2 = 4.4v to 5.25v (car application) typical values at v vs1 = v vs2 = 3v (battery application) and t amb = 25c unless otherwise specified. v vsint = 2.15v to 5.25v can be used independent from v vs1 and v vs2 in the case the microcontroller uses an different supply voltage. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 96 4829c?rke?09/05 ATA5823/ata5824 23. package information 22. ordering information extended type number package remarks ATA5823-plqw qfn48 7 mm x 7 mm, pb-free ata5824-plqw qfn48 7 mm x 7 mm, pb-free 97 4829c?rke?09/05 ATA5823/ata5824 24. table of contents features .............. ................ ................ ............... .............. .............. ............ 1 applications ......... ................ .............. ............... .............. .............. ............ 2 benefits................... .............. .............. ............... .............. .............. ............ 2 general description ............. .............. ............... .............. .............. ............ 2 1 pin configuration ..... ................ ................ ................. ................ ............... 3 2 typical key fob application for bi-direct ional rke .......... ........... ........ 6 3 typical car application for bi-directional rke ............... ............ .......... 7 4 typical key fob application for full-dup lex peg ............. ........... ........ 8 5 typical car application for full-duplex peg ........... ................. ............ 9 6 rf transceiver in ha lf-duplex mode ......... ................ ................. .......... 10 7 rf transceiver in full-duplex mode ...... ................. ................ ............. 25 8 xto ................ ................ ................. ................ ................. .............. .......... 27 9 power supply ........... ................ ................ ................. ................ ............. 31 10 microcontroller interface .... .............. ............... .............. .............. .......... 35 11 digital control logic ......... ................ ............... .............. .............. .......... 35 12 transceiver configuration . .............. ............... .............. .............. .......... 47 13 operation modes ............... ................ ............... .............. .............. .......... 52 14 absolute maximum ratings .. .............. .............. .............. .............. ........ 71 15 thermal resistance ............ .............. ............... .............. .............. .......... 71 16 electrical characteristics: general ........ ................. ................ ............. 72 17 electrical characteristic: battery applicat ion ................. ............ ........ 86 18 electrical characteristics: car application .............. ................. .......... 88 19 digital timing characteristi cs .............. .............. .............. ............ ........ 90 20 digital port characteristics .............. ............... .............. .............. .......... 94 21 ordering information ........ ................ ............... .............. .............. .......... 96 22 package information ........... .............. ............... .............. .............. .......... 96 printed on recycled paper. 4829c?rke?09/05 ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, everywhere you are ? and others, are registered trade- marks or trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature |
Price & Availability of ATA5823
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |